A functional instruction mix and some related topics

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A functional instruction mix and some related topics

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Joint International Conference on Measurement and Modeling of Computer Systems archive
Proceedings of the 1976 ACM SIGMETRICS conference on Computer performance modeling measurement and evaluation table of contents

Cambridge, Massachusetts, United States

Pages: 145 - 153

Year of Publication: 1976

Author

James H. Hughes

Sponsors

IFIP WG 7.3 : IFIP WG 7.3
SIGMETRICS: ACM Special Interest Group on Measurement and Evaluation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 2

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abstract references cited by index terms peer to peer

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ABSTRACT

In recent years the use of instruction mixes to define measures of relative computational power has diminished. This paper will describe how a systemic functional mix of much greater power and complexity than the traditional Gibson Mix was derived, then employed effectively in solving problems which arise in central processor definition and design. Some extensions of the basic technique are also covered, which include decomposition into fractional mixes as well as the study of instruction doublets and triplets.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Gibson J.C. The Gibson Mix IBM System Development Division Report, TR 00.2043 Poughkeepsie, New York, 1970
	2	James Hughes , David Cronshaw, On using a hardware monitor as an intelligent peripheral, ACM SIGMETRICS Performance Evaluation Review, v.2 n.4, p.3-19, December 1973 [doi>10.1145/1113650.1113651]
	3	Xerox SIGMA 7 Computer Reference Manual, 90 0950 Xerox Publication, El Segundo, California, 1971

CITED BY 2

	Bernard L. Peuto , Leonard J. Shustek, An instruction timing model of CPU performance, 25 years of the international symposia on Computer architecture (selected papers), p.152-165, June 27-July 02, 1998, Barcelona, Spain
	Bernard L. Peuto , Leonard J. Shustek, An instruction timing model of CPU performance, ACM SIGARCH Computer Architecture News, v.5 n.7, p.165-178, March 1977