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Reconfigurable Pipeline Systems
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Proceedings of the 1978 annual conference table of contents
Washington, D.C., United States
Pages: 86 - 92  
Year of Publication: 1978
ISBN:0-89791-000-1
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ACM: Association for Computing Machinery
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ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 25,   Citation Count: 3
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ABSTRACT

Systems with pipeline processing capabilities, processors whose computational subsystems are divided into several distinct stages, each of which may be working with an independent set of data at the same instant of time, are one attractive solution to the demand for faster and more cost effective computers. In addition, several of the existing pipelined machines have facilities for a limited amount of restructuring of available resources to provide a system which is more suitable for the efficient execution of a particular problem. The amount of restructuring, or reconfiguration, varies from system to system. The type of reconfiguration, either a reconfiguration of an actual functional unit or a reconfiguration of the information flow between several functional units, varies as well. The reconfigurable aspects of the architecture of several pipelined machines are presented. Performance gains when restructuring is allowed are also examined. Finally, there is a discussion of some possible future reconfigurable pipeline systems.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Anderson, D. W., Sparacio, F. J. and Tomasulo, R. M., IBM System 360 Model 91, machine philosophy and instruction handling, IBM Journal of Research and Development, p. 8, (Jan. 1967).
 
2
Baer, Jean-Loup, Multiprocessing systems, IEEE Transactions on Computers, Vol. C-25, No. 12, p. 1271, (Dec. 1976).
 
3
Chen, T. C., Overlap and pipeline processing, in Introduction to Computer Architecture, H. S. Stone, Ed., (SRA, Chicago, IL, 1975).
 
4
Chen, T. C., Parallelism, pipelining and computer efficiency, Computer Design, p. 69 (Jan. 1971).
 
5
Davidson, E. S., The Design and Control of Pipeline Function Generators, (Stanford Report, Stanford University, 1972).
 
6
Estrin, G., et al, Parallel processing in a restructurable computer system, IEEE Transactions on Computers, Vol. EC-12, p. 747, (Dec. 1963).
 
7
Flynn, M. J., Very high-speed computing systems, Proceedings of the IEEE, p. 1901, (IEEE, NY, 1966).
 
8
Hallin, T. G. and Flynn, M. J., Pipelining of arithmetic functions, IEEE Transactions on Computers, Vol. C-21, No. 9, p. 880, (Aug. 1972).
 
9
 
10
Hintz, R. G. and Tate, D. P., Control Data STAR-100 processor design, COMPCON72, p. 1, (IEEE, NY, 1972).
 
11
Ibbett, R. N., The MU5 instruction pipeline, Computer Journal, Vol. 15, p. 43, (1972).
12
 
13
Irwin, M. J., An Arithmetic Unit for On-Line Computation, Report No. UIUCDCS-R-77-873, (Department of Computer Science, University of Illinois, Urbana, May 1977).
14
 
15
Johnson, P. M., An introduction to vector processing, Computer Design, p. 89, (Feb. 1978).
 
16
Li, H. F., Scheduling trees in parallel/pipelined processing environments, IEEE Transactions on Computers, Vol. C-26, No. 11, p. 1101, (Nov. 1977).
17
18
 
19
Reddi, S. S. and Feustel, E. A., A restructurable computer system, IEEE Transactions on Computers, Vol. C-27, No. 1, p. 1, (Jan. 1978).
20
21
 
22
Watson, W. J., The Texas Instruments advanced scientific computer, COMPCON72, p. 291, (IEEE, NY, 1972).



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