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A logic simulation machine
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Source International Symposium on Computer Architecture archive
Proceedings of the 9th annual symposium on Computer Architecture table of contents
Austin, Texas, United States
Pages: 148 - 157  
Year of Publication: 1982
Also published in ...
Authors
M. Abramovici  Bell Laboratories, Naperville, IL
Y. H. Levendel  Bell Laboratories, Naperville, IL
P. R. Menon  Bell Laboratories, Naperville, IL
Sponsors
IEEE-CS : Computer Society
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 6,   Citation Count: 1
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ABSTRACT

Special-purpose CAD hardware is increasingly being considered as a means to meet the challenge posed to conventional (software-based) CAD tools by the growing complexity of VLSI circuits. In this paper we describe the architecture of a logic simulation machine employing distributed and parallel processing. Our architecture can accommodate different levels of modeling ranging from simple gates to complex functions, and support timing analysis. We estimate that simulation implemented by the proposed special-purpose hardware will be between 10 and 60 times faster than currently used software algorithms running on general-purpose computers. With the available technology, a throughput of 1,000,000 gate evaluations/second can be achieved.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Collaborative Colleagues:
M. Abramovici: colleagues
Y. H. Levendel: colleagues
P. R. Menon: colleagues

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