Decoupled access/execute computer architectures

ABSTRACT

An architecture for improving computer performance is presented and discussed. The main feature of the architecture is a high degree of decoupling between operand access and execution. This results in an implementation which has two separate instruction streams that communicate via queues. A similar architecture has been previously proposed for array processors, but in that context the software is called on to do most of the coordination and synchronization between the instruction streams. This paper emphasizes implementation features that remove this burden from the programmer. Performance comparisons with a conventional scalar architecture are given, and these show that considerable performance gains are possible. Single instruction stream versions, both physical and conceptual, are discussed with the primary goal of minimizing the differences with conventional architectures. This would allow known compilation and programming techniques to be used. Finally, the problem of deadlock in such a system is discussed, and one possible solution is given.

REFERENCES

• 1: Flynn, M. J., "Very High-Speed Computing Systems," Proceedings of the IEEE, Vol. 54, No. 12, pp. 1901-1909, December 1966.
• 2: Riseman, E. M. and C. C. Foster, "Percolation of Code to Enhance Parallel Dispatching and Execution," IEEE Trans. on Computers, Vol. C-21, No. 12, pp. 1411-1415, December 1972.
• 3: Tjaden, G. S. and M. J. Flynn, "Detection and Parallel Execution of Independent Instructions," IEEE Trans. on Computers, Vol. C-19, No. 10, pp. 889-895, October 1970.
• 4: J. E. Thornton, Design of a Computer—The Control Data 6600, Scott Foresman & Co, 1970
• 5: Anderson, D. W., F. J. Sparacio, and R. M. Tomasulo, "The IBM, System/360 Model 91: Machine Philosophy and Instruction Handling," IBM Journal of Research and Development, pp. 8-24, January 1967
• 6: Werner Buchholz, Planning a computer system: Project Stretch, McGraw-Hill, Inc., Hightstown, NJ, 1962
• 7: Cohler, E. U. and J. E. Storer, "Functionally Parallel Architecture for Array Processors," Computer, Vol. 14, No. 9, pp. 28-36, September 1981.
• 8: McMahon, F. H., "FORTRAN CPU Performance Analysis," Lawrence Livermore Laboratories, 1972.
• 9: CRAY-1 Computer Systems, Hardware Reference Manual, Cray Research, Inc., Chippewa Falls, WI, 1979.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: System architectures

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Single-instruction-stream, multiple-data-stream processors (SIMD)

General Terms:
Design