A control processor for a reconfigurable array computer

ABSTRACT

The problems of resource allocation, configuration and reconfiguration and network control must be solved before reconfigurable array computers can be effectively utilized. The interconnection networks proposed for these systems vary so that there has been no common or optimal solution proposed to these problems. This paper defines and describes the objectives, design, implementation and use of a network controller for a reconfigurable array computer, the Texas Reconfigurable Array Computer (TRAC). The objectives for the network controller are defined by management of the system state, the requirements of the operating system for functionality and the interface the network presents to the operating system. These objectives may be expected to have at least some commonality across most reconfigurable network architectures. The structure of the network controller given herein may offer guidance for development of controllers for other reconfigurable network architectures.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS
      C.2.1 Network Architecture and Design

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.2 Input/Output Devices
          Subjects: Channels and controllers
      B.4.3 Interconnections (subsystems)

General Terms:
Design