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Design-For-Debug in Hardware/Software Co-Design
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Source International Conference on Hardware Software Codesign archive
Proceedings of the 5th International Workshop on Hardware/Software Co-Design table of contents
Page: 35  
Year of Publication: 1997
ISBN:0-8186-7895-X
Authors
H. P. E. Vranken  Eindhoven University of Technology, Dep. of Electrical Engineering
M. P. J. Stevens  Eindhoven University of Technology, Dep. of Electrical Engineering
M. T. M. Segers  Eindhoven University of Technology, Dep. of Electrical Engineering and Philips Semiconductors, Eindhoven, Netherlands
Sponsors
SIGSOFT: ACM Special Interest Group on Software Engineering
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Computer Society  Washington, DC, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 13,   Citation Count: 1
Additional Information:

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ABSTRACT

The increasing complexity of hardware/software systems is handled effectively by hardware/software codesign methods. However, the debugging of hardware/software systems is still a very troublesome process. This is mainly due to the limited accessibility to the internals of embedded hardware/software systems. Debugging is also hindered by the nature of the design errors encountered during hardware/software debugging.We present a structured design-for-debug strategy to address the problems of hardware/software debugging. Our design-for-debug strategy is an integral part of hardware/software codesign. Furthermore, we re-use the hardware design-for-test facilities to reduce the overhead costs of design-for-debug. Two examples are provided to illustrate our design-for-debug strategy.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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[1] Rapid Prototyping of Application-Specific Signal Processors (RASSP). http://rassp.scra.org.
 
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[2] IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. IEEE, 1990.
 
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[3] IEEE 1149.5 Standard Module Test and Maintenance Bus. IEEE, 1995.
 
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[4] M. Abramovici, M. Breuer, and A. Friedman. Digital Systems Testing and Testable Design - Revised Printing. IEEE Press, 1995.
 
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[7] P. Fleming and D. McClean. Scan-based design verification - an alternative approach. ATE and Instrumentation Conference West, 1990.
 
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[9] A. Halliday, G. Young, and A. Crouch. Prototype testing simplified by scannable buffers and latches. IEEE Proceedings International Test Conference, pages 174-181, 1989.
 
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[12] D. Verkest, K. van Rompaey, I. Bolsens, and H. de Man. Coware - a design environment for heterogeneous hard-ware/software systems. Design Automation for Embedded Systems, 1(4): 357-386, October 1996.
 
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Collaborative Colleagues:
H. P. E. Vranken: colleagues
M. P. J. Stevens: colleagues
M. T. M. Segers: colleagues