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Physical synthesis methodology for high performance microprocessors
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th annual Design Automation Conference table of contents
Anaheim, CA, USA
SESSION: Highlights of ISSCC and the design of state-of-the-art microprocessors table of contents
Pages: 696 - 701  
Year of Publication: 2003
ISBN:1-58113-688-9
Authors
Yiu-Hing Chan  IBM Server Group, Poughkeepsie, NY
Prabhakar Kudva  IBM TJ Watson Research Center, Yorktown Heights, NY
Lisa Lacey  IBM TJ Watson Research Center, Yorktown Heights, NY
Greg Northrop  IBM TJ Watson Research Center, Yorktown Heights, NY
Thomas Rosser  IBM Server Group, Austin, TX
Sponsor
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

Integrated logic synthesis and physical design (physical synthesis) continues to play a very important role in high performance microprocessor design methodologies. In this paper, we present the integrated physical synthesis timing closure methodology used in the current generation microprocessors. Physical synthesis techniques were aggressively used as part of logic and placement optimizations for performance, power and area. The design turn around times were significantly reduced and timing convergence was consistently acheived.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Averill, R. M. et al.. Chip integration methodology for the ibm S/390 G5 and G6 custom microprocessors. IBM Journal of Research and Development 43, 5 (1999), 681--707.
 
2
3
4
 
5
Hathaway, D., Abato, R., Drumm, A., and van Ginneken, L. Incremental timing analysis. Tech. rep., 1996. IBM, U.S. patent 5,508,937.
 
6
 
7
K. L. Shepard, V. Narayanan, and R. Rose. Harmony: Static noise analysis of deep submicron digital integrated circuits. IEEE Transactions on Computer-Aided Design 18, 8 (1999), 1132--1150.
 
8
Kudva, P. Continuous optimizations in synthesis: The discretization problem. In International Workshop in Logic Synthesis (1998), pp. 188--191.
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Leobandung, E. et al. High performance 0.18 mm SOI CMOS technology. In IEEE IEDM Technical Digest (1999), IEEE Computer Society Press, pp. 679--682.
 
12
13
 
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Warnock, J. D. et al. The circuit and physical design for the power4 microprocessor. IBM Journal of Research and Development 46, 1 (2002), 27--53.


Collaborative Colleagues:
Yiu-Hing Chan: colleagues
Prabhakar Kudva: colleagues
Lisa Lacey: colleagues
Greg Northrop: colleagues
Thomas Rosser: colleagues

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