| Physical synthesis methodology for high performance microprocessors |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 40th annual Design Automation Conference
table of contents
Anaheim, CA, USA
SESSION: Highlights of ISSCC and the design of state-of-the-art microprocessors
table of contents
Pages: 696 - 701
Year of Publication: 2003
ISBN:1-58113-688-9
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Authors
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Yiu-Hing Chan
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IBM Server Group, Poughkeepsie, NY
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Prabhakar Kudva
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IBM TJ Watson Research Center, Yorktown Heights, NY
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Lisa Lacey
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IBM TJ Watson Research Center, Yorktown Heights, NY
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Greg Northrop
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IBM TJ Watson Research Center, Yorktown Heights, NY
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Thomas Rosser
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IBM Server Group, Austin, TX
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Downloads (6 Weeks): 1, Downloads (12 Months): 19, Citation Count: 4
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ABSTRACT
Integrated logic synthesis and physical design (physical synthesis) continues to play a very important role in high performance microprocessor design methodologies. In this paper, we present the integrated physical synthesis timing closure methodology used in the current generation microprocessors. Physical synthesis techniques were aggressively used as part of logic and placement optimizations for performance, power and area. The design turn around times were significantly reduced and timing convergence was consistently acheived.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Averill, R. M. et al.. Chip integration methodology for the ibm S/390 G5 and G6 custom microprocessors. IBM Journal of Research and Development 43, 5 (1999), 681--707.
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[doi> 10.1145/309847.309979]
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Wilm Donath , Prabhakar Kudva , Leon Stok , Lakshmi Reddy , Andrew Sullivan , Kanad Chakraborty , Paul Villarrubia, Transformational placement and synthesis, Proceedings of the conference on Design, automation and test in Europe, p.194-201, March 27-30, 2000, Paris, France
[doi> 10.1145/343647.343732]
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L. Stok , D. S. Kung , D. Brand , A. D. Drumm , L. N. Reddy , N. Hieter , D. J. Geiger , H. H. Chao , P. J. Osler , A. J. Sullivan, BooleDozer: logic synthesis for ASICs, IBM Journal of Research and Development, v.40 n.4, p.407-430, July 1996
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CITED BY 4
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Victor Zyuban , Sameh W. Asaad , Thomas W. Fox , Anne-Marie Haen , Daniel Littrell , Jaime H. Moreno, Design methodology for semi custom processor cores, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
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