Test generation for designs with multiple clocks

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Test generation for designs with multiple clocks

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th annual Design Automation Conference table of contents

Anaheim, CA, USA

SESSION: Test and diagnosis for complex designs table of contents

Pages: 662 - 667

Year of Publication: 2003

ISBN:1-58113-688-9

Authors

Xijiang Lin	Mentor Graphics Corp., Wilsonville, OR
Rob Thompson	Mentor Graphics Corp., Wilsonville, OR

Sponsor

ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 10, Citation Count: 4

Additional Information:

abstract references cited by index terms collaborative colleagues peer to peer

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ABSTRACT

To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize multiple clocks in the design effectively and efficiently in order to dramatically reduce test pattern count without sacrificing fault coverage or causing clock skew problem. This is achieved by pulsing multiple non-interactive clocks simultaneously and applying a clock concatenation technique. Experimental results on several industrial circuits show significant test pattern count reduction by using the proposed test generation procedures.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	"Designs with Multiple Clock Domains: Avoiding Clock Skew and Reducing Pattern Count Using DFTAdvisor™ and FastScan™," Technical White Paper, in http://www.mentor.com/dft.
	2	R. Press and R. Illman, "ATPG Pattern Compaction: The Next Wave," Technical White Paper, in http://www.mentor.com/dft.
	3	Vishal Jain , John Waicukauski, Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique, Proceedings of the 2002 IEEE International Test Conference, p.148, October 07-10, 2002
	4	"ATPG Tools Reference Manual - FastScan, FlexTest, and TestKompress," Mentor Graphics Corp., 2002.

CITED BY 4

	Qiang Xu , Nicola Nicolici , Krishnendu Chakrabarty, Multi-frequency wrapper design and optimization for embedded cores under average power constraints, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	A. Sehgal , K. Chakrabarty, Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.88-93, November 06-10, 2005, San Jose, CA
	Anuja Sehgal , Sudarshan Bahukudumbi , Krishnendu Chakrabarty, Power-aware SoC test planning for effective utilization of port-scalable testers, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.3, p.1-19, July 2008
	Matthias Beck , Olivier Barondeau , Martin Kaibel , Frank Poehl , Xijiang Lin , Ron Press, Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality, Proceedings of the conference on Design, Automation and Test in Europe, p.56-61, March 07-11, 2005