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Three extensions to register integration
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Source International Symposium on Microarchitecture archive
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture table of contents
Istanbul, Turkey
SESSION: Superscalar design table of contents
Pages: 37 - 47  
Year of Publication: 2002
ISBN ~ ISSN:1072-4451 , 0-7695-1859-1
Authors
Vlad Petric  University of Pennsylvania
Anne Bracy  University of Pennsylvania
Amir Roth  University of Pennsylvania
Sponsors
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
: IEEE TC-uArch
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 6,   Citation Count: 5
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ABSTRACT

Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash reuse, the integration mechanism can exploit more reuse scenarios. Here, we describe three extensions to the original design that expand its applicability and boost its performance impact. First, we extend squash reuse to general reuse. Whereas squash reuse maintains the concept of an instruction instance "owning" its output register, we allow multiple instructions to simultaneously share a single register. Next, we replace the PC indexing scheme with an opcode-based indexing scheme that exposes more integration opportunities. Finally, we introduce an extension called reverse integration in which we speculatively create integration entries for the inverses of operations---for instance, when renaming an add, we create an entry for the inverse subtract. Reverse integration allows us to reuse operations that the program itself has not executed yet. We use reverse integration to implement speculative memory bypassing for stack-pointer based loads (register fills and restores).Our evaluation shows that these extensions increase the integration rate---the number of retired instructions that integrate older results and bypass the execution engine---to an average of 15% on the SPEC2000 integer benchmarks. On a 4-way superscalar processor with an aggressive memory system, this translates into an average IPC improvement of 7%. The fact that integrating instructions completely bypass the execution engine raises the possibility of using integration as a low-complexity substitute for execution bandwidth and issue buffering. Our experiments show that such a trade-off is possible, enabling a range of IPC/complexity designs.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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P. Glaskowsky. "Pentium 4 (Partially) Previewed." Microprocessor Report, 14(8), Aug. 2000.
 
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S. Jourdan, R. Ronen, M. Bekerman, B. Shomar, and A. Yoaz. "A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification." MICRO-31, Dec. 1998.
 
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S. Onder and R. Gupta. "Load and Store Reuse using Register File Contents." ICS-15, Jan. 2001.
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A. Roth and G. Sohi. "Squash Reuse via a Simplified Implementation of Register Integration." JILP-4, 2002.
 
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Collaborative Colleagues:
Vlad Petric: colleagues
Anne Bracy: colleagues
Amir Roth: colleagues