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Topologically constrained logic synthesis
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Source International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
Pages: 679 - 686  
Year of Publication: 2002
ISBN ~ ISSN:1092-3152 , 0-7803-7607-2
Authors
Subarnarekha Sinha  University of California at Berkeley, Berkeley, CA
Alan Mishchenko  Portland State University, Portland, OR
Robert K. Brayton  University of California at Berkeley, Berkeley, CA
Sponsors
: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

SPFDs, a mechanism for expressing flexibility during logic synthesis, were first introduced for FPGA synthesis. They were then extended to general, combinational Boolean networks and later the concept of sequential SPFDs was introduced. In this paper, we explore the idea of using SPFDs for functional decomposition. A new type of functional decomposition called topologically constrained decomposition is introduced. An algorithm is provided for solving this problem using SPFDs. Preliminary experimental results are encouraging and indicate the feasibility of the approach. A scheme is also presented for generating instances of the topologically constrained decomposition problem.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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E.M. Sentovich and R.K. Brayton. Multiple Boolean Relations. In International Workshop on Logic Synthesis, May 1993.
 
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R.L. Ashenhurst. The Decomposition of Switching Functions. In International Symposium on Theory of Switching Functions, 1959.
 
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M. Perkowski and S. Grygiel. A Survey of literature on Functions Decomposition. Technical Report, Department of Electrical Engineering, Portland State University, 1995.
 
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S. Sinha and R. Brayton. Improved Robust SPFD Computations. In International Workshop on Logic Synthesis, Jun 2001.
 
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A. Mishchenko and R.K. Brayton. Simplification of Non-Deterministic Multi-Valued Networks. Submitted to International Workshop on Logic Synthesis, Jun 2002.
 
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P. Chong, Y. Jiang, S. Khatri, F. Mo, S. Sinha and R. Brayton. Don't Care Wires in Logical/Physical Design. In International Workshop on Logic Synthesis, Jun 2000.

Collaborative Colleagues:
Subarnarekha Sinha: colleagues
Alan Mishchenko: colleagues
Robert K. Brayton: colleagues

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