An energy-conscious algorithm for memory port allocation

ABSTRACT

Multiport memories are extensively used in modern system designs because of the performance advantages they offer. The increased memory access throughput could lead to significantly faster schedules in behavioral synthesis. However, they also have an associated area and energy penalty. We describe a technique for mapping data accesses to multiport memories during behavioral synthesis that results in significantly better energy characteristics than an unoptimized multiport design. The technique consists of an initial colouring of the array access nodes in the data flow graph based on spatial locality, followed by attempts to consecutively access memory locations with the same colour on the same port. Our experiments on several applications indicate a significant reduction in address bus switching activity, leading to an overall energy reduction over an unoptimized design, while still maintaining a performance advantage over a single-port solution.

REFERENCES

• 1: E. Musoll , J. Cortadella, High-level synthesis techniques for reducing the activity of functional units, Proceedings of the 1995 international symposium on Low power design, p.99-104, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224099]
• 2: P. R. Panda , F. Catthoor , N. D. Dutt , K. Danckaert , E. Brockmeyer , C. Kulkarni , A. Vandercappelle , P. G. Kjeldsberg, Data and memory optimization techniques for embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.149-206, April 2001 [doi>10.1145/375977.375978]
• 3: Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000 [doi>10.1145/335043.335044]
• 4: Precti Ranjan Panda , Nikil D. Dutt, Low-power memory mapping through reducing address bus activity, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.3, p.309-320, Sept. 1999 [doi>10.1109/92.784092]
• 5: Luca Benini , Giovanni De Mecheli , Enrico Macii , Massimo Poncino , Stefano Quer, Power optimization of core-based systems by address bus encoding, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.4, p.554-562, Dec. 1998 [doi>10.1109/92.736127]
• 6: M. Kandemir , N. Vijaykrishnan , M. J. Irwin , W. Ye, Influence of compiler optimizations on system power, Proceedings of the 37th conference on Design automation, p.304-307, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337425]
• 7: P. R. Panda et al., "Local memory exploration and optimization in embedded systems," IEEE TCAD, Jan. 1999.
• 8: Wen-Tsong Shiue , Chaitali Chakrabarti, Memory exploration for low power, embedded systems, Proceedings of the 36th ACM/IEEE conference on Design automation, p.140-145, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309902]
• 9: M. Balakrishnan et al., "Allocation of multiport memories in data path synthesis," IEEE TCAD, Apr. 1988.
• 10: Taewhan Kim , C. L. Liu, Utilization of multiport memories in data path synthesis, Proceedings of the 30th international conference on Design automation, p.298-302, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164900]
• 11: Preeti R. Panda , Nikil D. Dutt, Behavioral Array Mapping into Multiport Memories Targeting Low Power, Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, p.268, January 04-07, 1997

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

Additional Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

  E. Data
  E.1 DATA STRUCTURES
      Subjects: Graphs and networks

General Terms:
Experimentation, Performance, Standardization, Theory