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Simplification of non-deterministic multi-valued networks
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Source International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
Pages: 557 - 562  
Year of Publication: 2002
ISBN ~ ISSN:1092-3152 , 0-7803-7607-2
Authors
Alan Mishchenko  Portland State University, Portland, OR
Robert Brayton  University of California, Berkeley, CA
Sponsors
: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 2,   Downloads (12 Months): 10,   Citation Count: 6
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ABSTRACT

We discuss the simplification of non-deterministic MV networks and their internal nodes using internal flexibilities. Given the network structure and its external specification, the flexibility at a node is derived as a non-deterministic MV relation. This flexibility is used to simplify the node representation and enhance the effect of Boolean resubstitution. We show that the flexibility derived is maximum. The proposed approach has been implemented and tested in MVSIS [16]. Experimental results show that it performs well on a variety of MV and binary benchmarks.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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R. K. Brayton. Compatible Observability Don't-Cares Revisited. Proc. of IWLS'01. pp. 121--126.
 
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J.-H. Jiang, Y. Jiang, and R. Brayton. An Implicit Method for Multi-Valued Network Encoding. Proc. of IWLS'01, pp. 127--131.
 
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T. Hanyu, M. Kameyama. A 200 MHz Pipelined Multiplier Using 1.5 V-Supply Multiple-Valued MOS Current-Mode Circuits with Dual-Rail Source-Coupled Logic. IEEE J.Solid State Circuits, vol. 30, no 11, pp. 1239--1245, Nov. 1995.
 
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A. Kondratyev. Design of Delay-Insensitive Combinational Logic through MV-Synthesis. Unpublished manuscript.
 
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A. Mishchenko. An Experimental Evaluation of Algorithms for Computation of Internal Don't-Cares in Boolean Networks. Technical Report. Sept. 2001. http://www.ee.pdx.edu/~alanmi/research/net/DCcomparison.pdf
 
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A. Mishchenko, R. K. Brayton. A Boolean Paradigm in Multi-Valued Logic Synthesis. Proc. IWLS '02, June 2002.
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S. Minato. Fast Generation of Irredundant Sum-of-Products Forms from Binary Decision Diagrams. Proc. of SASIMI'92 (Synthesis and Simulation Meeting and International Interchange), Kobe, Japan, pp. 64--73.
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MVSIS Group. MVSIS. UC Berkeley. http://www-cad.eecs.berkeley.edu/mvsis/
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H. Savoj. Improvements in Technology Independent Optimization of Logic Circuits. Proc. of IWLS'97.
 
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E. Sentovich, et al. "SIS: A System for Sequential Circuit Synthesis", Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, Univ. of California, Berkeley, 1992.
 
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Y. Watanabe, L. Guerra and R. K. Brayton. Logic Optimization with Multi-Output Gates. Proc. ICCD '93, pp. 416--420.


Collaborative Colleagues:
Alan Mishchenko: colleagues
Robert Brayton: colleagues

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