On automatic generation of RTL validation test benches using circuit testing techniques

ABSTRACT

In this paper, we examine how good validation test benches can be automatically generated starting from the RTL description of a circuit. We develop our methodology based on extensive experiments performed with several popular benchmarks as well as industrial circuits.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.0 GENERAL

Additional Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES
      B.2.3 Reliability, Testing, and Fault-Tolerance**
  B.7 INTEGRATED CIRCUITS
      B.7.3 Reliability and Testing**
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Experimentation, Reliability, Verification

Keywords:
ATPG, OCCOM, RTL ATPG, RTL testing, branch coverage, code coverage, coverage metrics, design validation, fault coverage, generation, path coverage, small validation, test, test sets, testbench, testing, toggle coverage, universal test sets