Zero overhead watermarking technique for FPGA designs

ABSTRACT

FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing watermarking and fingerprinting techniques successfully embed identification information into FPGA designs to deter IP infringement. However, such methods incur timing and/or resource overhead, unpredictable at times, which causes performance degradation. In this paper, we propose a new FPGA watermarking technique that guarantees zero design overhead.Our approach consists of two phases. First we design as usual to obtain the best, possible, quality IP. Then we map the required signature to additional timing constraints on carefully selected nets and redo a small portion of the design (e.g. place and route). The FPGA configuration bitstream for the resulting watermarked design will be significantly different from the original design, which provides us with a strong proof of authorship. The watermarking technique has zero design overhead because it is developed to maintain the performance of the design from the first phase. This is demonstrated by applying the proposed technique on several real-life FPGA designs, which range in size from a few thousand to more than two million gates, on Xilinx devices.

REFERENCES

• 1: Andrew E. Caldwell , Hyun-Jin Choi , Andrew B. Kahng , Stefanus Mantik , Miodrag Potkonjak , Gang Qu , Jennifer L. Wong, Effective iterative techniques for fingerprinting design IP, Proceedings of the 36th ACM/IEEE conference on Design automation, p.843-848, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310083]
• 2: Inki Hong , Miodrag Potkonjak, Behavioral synthesis techniques for intellectual property protection, Proceedings of the 36th ACM/IEEE conference on Design automation, p.849-854, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310085]
• 3: Andrew B. Kahng , Darko Kirovski , Stefanus Mantik , Miodrag Potkonjak , Jennifer L. Wong, Copy detection for intellectual property protection of VLSI designs, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.600-605, November 07-11, 1999, San Jose, California, United States
• 4: A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, et al., "Constraint-Based Watermarking Techniques for Design IP Protection", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1236--1252, October 2001.
• 5: Darko Kirovski , Yean-Yow Hwang , Miodrag Potkonjak , Jason Cong, Intellectual property protection by watermarking combinational logic synthesis solutions, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.194-198, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288609]
• 6: Darko Kirovski , David Liu , Jennifer Wong , Miodrag Potkonjak, Forensic engineering techniques for VLSI CAD tools, Proceedings of the 37th conference on Design automation, p.581-586, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337584]
• 7: John Lach , William H. Mangione-Smith , Miodrag Potkonjak, Robust FPGA intellectual property protection through multiple small watermarks, Proceedings of the 36th ACM/IEEE conference on Design automation, p.831-836, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310080]
• 8: John Lach , William H. Mangione-Smith , Miodrag Potkonjak, Signature hiding techniques for FPGA intellectual property protection, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.186-189, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288606]
• 9: J. Lach, W. H. Mangione-Smith, M. Potkonjak, "FPGA Fingerprinting Techniques for Protecting Intellectual Property", Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, pp. 299--302, May 1998.
• 10: Miles Ohlrich , Carl Ebeling , Eka Ginting , Lisa Sather, SubGemini: identifying subcircuits using a fast subgraph isomorphism algorithm, Proceedings of the 30th international conference on Design automation, p.31-37, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164556]
• 11: Arlindo L. Oliveira, Robust techniques for watermarking sequential circuit designs, Proceedings of the 36th ACM/IEEE conference on Design automation, p.837-842, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310082]
• 12: Gang Qu , Miodrag Potkonjak, Fingerprinting intellectual property using constraint-addition, Proceedings of the 37th conference on Design automation, p.587-592, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337586]
• 13: Gang Qu, Publicly detectable techniques for the protection virtual components, Proceedings of the 38th conference on Design automation, p.474-479, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378565]
• 14: Joshua R. Smith , Barrett O. Comiskey, Modulation and Information Hiding in Images, Proceedings of the First International Workshop on Information Hiding, p.207-226, May 30-June 01, 1996
• 15: Performance Study of a Selective Encryption Scheme for the Security of Networked, Real-Time Video, Proceedings of the 4th International Conference on Computer Communications and Networks, p.2, September 20-23, 1995
• 16: K. W. Yip and T. S. Ng, "Partial-Encryption Technique for Intellectual Property Protection of FPGA-Based Products", IEEE Transactions on Consumer Electronics, pp. 183--190, February 2000.
• 17: Personal Communication with Chris Mead, Xilinx Inc.
• 18: Synopsys White Paper on FPGA solutions.
• 19: Virtex™-II Platform FPGA Data Sheet.
• 20: Virtual Socket Interface Alliance. "Intellectual Property Protection White Paper: Schemes, Alternatives and Discussion Version 1.0", September 2000.
• 21: Xilinx FPGA Reuse Methodology Manual, 2nd Edition.
• 22: High Energy Group, Physics Department, University of Maryland.
• 23: Benchmark Suite for Placement, CAD/VLSI Lab, National Tsinghua University. http://nthucad.cs.nthu.edu.tw/~ycchou/benchmark.
• 24: www.opencores.org.
• 25: www.xilinx.com.

INDEX TERMS

Primary Classification:
  K. Computing Milieux
  K.5 LEGAL ASPECTS OF COMPUTING
      K.5.1 Hardware/Software Protection

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays
  B.m MISCELLANEOUS
      Subjects: Design management

  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Design, Legal Aspects, Performance, Security

Keywords:
FPGA, IP protection, configuration bitstream, performance, place and route, timing analyzer, user constraint file, zero overhead