ACM Home Page
Please provide us with feedback. Feedback
Separated high-bandwidth and low-latency communication in the cluster interconnect Clint
Full text PdfPdf (235 KB)
Source Conference on High Performance Networking and Computing archive
Proceedings of the 2002 ACM/IEEE conference on Supercomputing table of contents
Baltimore, Maryland
Pages: 1 - 12  
Year of Publication: 2002
Authors
Hans Eberle  Sun Microsystems Laboratories
Nils Gura  Sun Microsystems Laboratories
Sponsors
IEEE-CS\DATC : IEEE Computer Society
ACM: Association for Computing Machinery
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
Bibliometrics
Downloads (6 Weeks): 0,   Downloads (12 Months): 11,   Citation Count: 1
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues   peer to peer  

Tools and Actions: Review this Article  

ABSTRACT

An interconnect for a high-performance cluster has to be optimized in respect to both high throughput and low latency. To avoid the tradeoff between throughput and latency, the cluster interconnect Clint has a segregated architecture that provides two physically separate transmission channels: A bulk channel optimized for high-bandwidth traffic and a quick channel optimized for low-latency traffic. Different scheduling strategies are applied. The bulk channel uses a scheduler that globally allocates time slots on the transmission paths before packets are sent off. This way collisions as well as blockages are avoided. In contrast, the quick channel takes a best-effort approach by sending packets whenever they are available thereby risking collisions and retransmissions.Simulation results clearly show the performance advantages of the segregated architecture. The carefully scheduled bulk channel can be loaded nearly to its full capacity without exhibiting head-of-line blocking that limits many networks while the quick channel provides low-latency communication even in the presence of high-bandwidth traffic.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
3
 
4
J. Duato, P. López, F. Silla: A High Performance Router Architecture for Interconnection Networks. Proc. Int. Conf. On Parallel Processing. 1996.
 
5
 
6
 
7
J. Hoffman: HIPPI-6400 Technology Dissemination. Proc. of SPIE, vol. 2917, 1996, pp. 442--430.
 
8
R. Horst, D. Garcia: Servernet SAN I/O Architecture. Hot Interconnects V Symposium, Stanford, Aug. 21--23, 1997.
 
9
M. Karol, M. Hluchyi, S. Morgan: Input versus Output Queuing on a Space-Division Packet Switch. IEEE Transactions on Communications, C-35(12):1347--1356, December 1987.
 
10
R. Kessler, J. Schwarzmeier: Cray T3D: A New Dimension for Cray Research. Proc. 38th IEEE Int. Computer Conf., 1993, pp. 176--182.
 
11
 
12
13
 
14
15
 
16
N. McKeown, C. Calamvokis, S. Chuang: A 2.5 Tb/s LCS Switch Core. Hot Chips 13, August 19--21 2001, Stanford, California.
 
17
 
18
 
19
National Committee for Information Technology Standardization: Scheduled Transfer Protocol (ST). Task Group btgt11.1, rev. 3.6, January 31, 2000, www.hippi.org.
 
20



Peer to Peer - Readers of this Article have also read: