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Tutorial: Compiling concurrent languages for sequential processors
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Source ACM Transactions on Design Automation of Electronic Systems (TODAES) archive
Volume 8 ,  Issue 2  (April 2003) table of contents
Pages: 141 - 187  
Year of Publication: 2003
ISSN:1084-4309
Author
Stephen A. Edwards  Columbia University, Amsterdam Avenue, New York
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 4,   Downloads (12 Months): 48,   Citation Count: 11
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ABSTRACT

Embedded systems often include a traditional processor capable of executing sequential code, but both control and data-dominated tasks are often more naturally expressed using one of the many domain-specific concurrent specification languages. This article surveys a variety of techniques for translating these concurrent specifications into sequential code. The techniques address compiling a wide variety of languages, ranging from dataflow to Petri nets. Each uses a different method, to some degree chosen to match the semantics of concurrent language. Each technique is considered to consist of a partial evaluator operating on an interpreter. This combination provides a clearer picture of how parts of each technique could be used in a different setting.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
Balarin, F., Chiodo, M., Giusto, P., Hsieh, H., Jurecska, A., Lavagno, L., Sangiovanni-Vincentelli, A., Sentovich, E. M., and Suzuki, K. 1999. Synthesis of software programs for embedded control applications. IEEE Trans. Comput. Aided Des. Integ. Circ. Syst. 18, 6 (June), 834--849.
 
3
Benveniste, A., Caspi, P., Edwards, S. A., Halbwachs, N., Guernic, P. L., and de Simone, R. 2003. The synchronous languages 12 years later. Proc. IEEE 91, 1 (Jan.), 64--83.
 
4
 
5
Berry, G. 1999. The constructive semantics of pure Esterel. Draft book.
 
6
Berry, G. 2000. The Esterel v5 Language Primer. Centre de Mathématiques Appliquées. Part of the Esterel compiler distribution.
 
7
 
8
 
9
Bertin, V., Poize, M., and Pulou, J. 1999. Une nouvelle méthode de compilation pour le language ESTEREL {A new method for compiling the Esterel language}. In Proceedings of GRAISyHM-AAA (Lille, France).
 
10
Bhattacharyya, S. S., Buck, J. T., Ha, S., Murthy, P. K., and Lee, E. A. 1993. A scheduling framework for minimizing memory requirements of multirate DSP systems represented as dataflow graphs. In Proceedings of the IEEE Workshop on VLSI Signal Processing VI. The Institute of Electrical and Electronics Engineers (IEEE), Veldhoven, The Netherlands, 188--196.
 
11
Bhattacharyya, S. S., Leupers, R., and Marwedel, P. 2000. Software synthesis and code generation for signal processing systems. IEEE Trans. Circ. Syst.---II: Analog Digital Signal Process. 47, 9 (Sept.), 849--875.
 
12
 
13
 
14
Bilsen, G., Engels, M., Lauwereins, R., and Peperstraete, J. A. 1995. Cyclo-static data flow. In Proceedings of the IEEE International Conference on Acoustics, Speech, & Signal Processing (ICASSP) (Detroit), 3255--3258.
 
15
Boussinot, F. and Doumenc, G. 1992. RC reference manual.
 
16
 
17
18
 
19
 
20
Buck, J. T. 1994. Static scheduling and code generation from dynamic dataflow graphs with integer-valued control streams. In Conference Record of the Twenty-Eighth Asilomar Conference on Signals, Systems & Computers. The Institute of Electrical and Electronics Engineers (IEEE), Pacific Grove, CA, 508--513.
21
22
23
 
24
Cortadella, J., Kondratyev, A., Lavagno, L., Massot, M., Moral, S., Passerone, C., Watanabe, Y., and Sangiovanni-Vincentelli, A. 1999. Task generation and compile-time scheduling for mixed data-control embedded software. Tech. Rep. LSI-99-47-R, Department of Software, Universitat Politècnica de Catalunya. November.
25
26
 
27
Edwards, S. A. 2002. An Esterel compiler for large control-dominated systems. IEEE Trans. Comput. Aided Des. Integ. Circ. Syst. 21, 2 (Feb.), 169--183.
28
29
30
 
31
Gonthier, G. 1988. Sémantiques et modèles d'exécution des langages réactifs synchrones; application à Esterel. {Semantics and models of execution of the synchronous reactive languages: application to Esterel}. Thèse d'informatique, Université d'Orsay.
 
32
 
33
 
34
Halbwachs, N., Caspi, P., Raymond, P., and Pilaud, D. 1991a. The synchronous data flow programming language LUSTRE. Proc. IEEE 79, 9 (Sept.), 1305--1320.
 
35
Halbwachs, N., Raymond, P., and Ratel, C. 1991b. Generating efficient code from data-flow programs. In Proceedings of the Third International Symposium on Programming Language Implementation and Logic Programming (PLILP), Lecture Notes in Computer Science, vol. 528, Springer-Verlag, Passau, Germany.
 
36
37
 
38
 
39
 
40
 
41
IEEE Computer Society. 1996. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language. IEEE Computer Society, New York, 1364--1995.
 
42
 
43
Kahn, G. 1974. The semantics of a simple language for parallel programming. In Information Processing 74: Proceedings of IFIP Congress 74, North-Holland, Stockholm, 471--475.
 
44
Kahn, G. and MacQueen, D. B. 1977. Coroutines and networks of parallel processes. In Information Processing 77: Proceedings of IFIP Congress 77. North-Holland, Toronto, 993--998.
 
45
 
46
Le Guernic, P., Gautier, T., Le Borgne, M., and Le Maire, C. 1991. Programming real-time applications with SIGNAL. Proc. IEEE 79, 9 (Sept.), 1321--1336.
 
47
 
48
Lee, E. A. and Messerschmitt, D. G. 1987b. Synchronous data flow. Proc. IEEE 75, 9 (Sept.), 1235--1245.
 
49
Lee, E. A. and Parks, T. M. 1995. Dataflow process networks. Proc. IEEE 83, 5 (May), 773--801.
50
 
51
52
 
53
 
54
 
55
Murata, T. 1989. Petri nets: Properties, analysis, and applications. Proc. IEEE 77, 4 (April), 541--580.
 
56
 
57
Petri, C. A. 1962. Kommunikation mit automaten. PhD Thesis, Institutes für Instrumentelle Mathematik, Bonn, Germany. In German.
 
58
Plotkin, G. D. 1981. A structural approach to operational semantics. Tech. Rep. DAIMI FN-19, Aarhus University, Åarhus, Denmark.
 
59
 
60
Sgroi, M., Lavagno, L., and Sangiovanni-Vincentelli, A. 1998. Quasi-static scheduling of free-choice Petri nets. Tech. Rep. UCB/ERL M98/9, University of California, Berkeley.
61
 
62
 
63
 
64
Simons, B. and Ferrante, J. 1993. An efficient algorithm for constructing a control flow graph for parallel code. Tech. Rep. TR--03.465, IBM, Santa Teresa Laboratory, San Jose, CA, February.
 
65
Steensgaard, B. 1993. Sequentializing program dependence graphs for irreducible programs. Tech. Rep. MSR-TR-93-14, Microsoft. October.
66
 
67
 
68
 
69
70
71
72
 
73

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"R. Clayton : Reviewer"

A reactive computation exchanges events with the environment in which the computation runs. Reactive computations execute with concurrency, but many compilers for reactive languages attempt to improve execution performance by generating purely seq  more...


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