A model for microarchitecture structure evaluation

ABSTRACT

This paper presents the specification and implementation of a model oriented primarily to the evaluation of the structure of microarchitectures. According to the model, target architectures are described as an oriented graph which is examined by search algorithms in order to find the minimum cost path required in the execution of a set of machine primitives. The model is very useful to determine the role of each target machine component: through the model it is possible to assess the effect of both including and removing architecture components on the overall performance of a machine being conceived. The paper shows the main aspects of the project, discusses the research potential of the model, and describes the current stage of the work.

REFERENCES

• BARB77: Mario R. Barbacci, "A Comparison of Register Transfer Language for Describing Computers and Digital Systems," IEEE Transactions on Computers, Vol. C-24, No. 2, February 1977.
• CLEE79: W. M/ vanCleemput, Computer hardware description languages and their applications, Proceedings of the 16th Conference on Design automation, p.554-560, June 25-27, 1979, San Diego, CA, United States
• FERN88: E. S.T. Fernandes, Microarchitecture modelling through ADL, Proceedings of the 21st annual workshop on Microprogramming and microarchitecture, p.100-104, November 28-December 02, 1988, San Diego, California, United States
• FISH81: Joseph A. Fisher," Trace Scheduling: A Technique for Global Microcode Compaction," IEEE Transactions on Computers, Vol. C-30, No. 7, July 1981.
• LAND80: David Landskov , Scott Davidson , Bruce Shriver , Patrick W. Mallett, Local Microcode Compaction Techniques, ACM Computing Surveys (CSUR), v.12 n.3, p.261-294, Sept. 1980 [doi>10.1145/356819.356822]
• LINN88: Joseph L. Linn, "Horizontal Microcode Compaction," in Microprogramming and Firmware Engineering Methods, Edited by Stanley Habib, Van Nostrand Reinhold, New York, 1988, pp. 381-431.
• PAWI85: A. Pawlak, "A Tutorial Guide to Modern Hardware Description Languages," Proceedings of the Euromicro 85, Brussel, September 1985.
• SANT89: Anna Dolejsi Santos, "Computer Architecture Evaluation," Technical Report ES/89, Programa de Engenharia de Sistemas e Computacao, COPPE- UFRJ, February 1989 (in Portuguese).
• SHIH88: L. Shih , C. A. Papachristou, Mapping of micro data flow computations on parallel microarchitectures, Proceedings of the 21st annual workshop on Microprogramming and microarchitecture, p.70-72, November 28-December 02, 1988, San Diego, California, United States
• SHIV77: Sajjan G. Shiva, "Computer Hardware Description Languages - A Tutorial," Proceedings of the IEEE, Vol. 17, No. 12, December 1977, pp. 1605-1615.
• UTH87: Augustus K. Uht , Constantine D. Polychronopoulos , John F. Kolen, On the combination of hardware and software concurrency extraction methods, Proceedings of the 20th annual workshop on Microprogramming, p.133-141, December 01-04, 1987, Colorado Springs, Colorado, United States [doi>10.1145/255305.255331]

INDEX TERMS

Primary Classification:
  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Sorting and searching

Additional Classification:
  B. Hardware
  B.1 CONTROL STRUCTURES AND MICROPROGRAMMING

  F. Theory of Computation
  F.1 COMPUTATION BY ABSTRACT DEVICES
      F.1.2 Modes of Computation
          Subjects: Parallelism and concurrency

General Terms:
Algorithms