Multiple operation memory structures

ABSTRACT

This paper describes architectures based on a new memory structure. Memory systems which can perform multiple transfers are described and issues in processor architecture are considered. A general model for memory operations is given, and the classical single transfer memory structures are described. Based on the generalized model, new structures which allow multiple transfers to be performed as a single processor operation are developed. Some architectural considerations at the processor level to support these kinds of memory systems are then discussed. The advantages and disadvantages of these new structures as compared to conventional memories are also discussed and a preliminary performance evaluation is done. This discussion generally refers to the random access, physical, main memory in the system, although many of the results are applicable to other storage devices.

REFERENCES

• 1: "Computer Architecture and Parallel Processing", Kai Hwang & Faye A. Briggs, McGraw Hill, 1984
• 2: John Mick , James Brick, Bit-Slice Microprocessor Design, McGraw-Hill, Inc., New York, NY, 1980
• 3: J. R. Goodman , W. C. Hsu, On the use of registers vs. cache to minimize memory traffic, Proceedings of the 13th annual international symposium on Computer architecture, p.375-383, June 02-05, 1986, Tokyo, Japan
• 4: M. Freeman, An architectural perspective on a memory access controller, Proceedings of the 14th annual international symposium on Computer architecture, p.214-223, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30375]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Memory design
      B.5.2 Design Aids
          Subjects: Simulation

General Terms:
Design, Performance