On inherent untestability of unaugmented microprogrammed control

ABSTRACT

Effective and efficient testing of the control part of a processor has remained a difficult problem. While several approaches have been proposed in the literature for handling unaugmented control parts, they involve questionable assumptions, and the results have not been encouraging. Here it is shown that unless some DFT (Design for Testability) approaches are taken, microprogrammed control is inherently a poorly testable structure. The considerations include lack of an elegant fault model, presence of components with low random testability, the length of a checking sequence and information-theoretic considerations. The design approaches must therefore include DFT augmentations and/or removal of sub-functional logic.

REFERENCES

• 1: R.L. Wadsack, "Design Verification and Testing of the WE32100 CPUs," IEEE DESIGN & Test, August 1984, pp. 66-75.
• 2: M.P. Klug, "Microprocessor Testing by Instruction Sequences Derived from Random Patterns," Proc. ITC, Sept. 1988, pp. 73-80.
• 3: J. Kuban and J. Salick, "Testability Features of the MC68020," Proc. ITC, Act. VS9, pp. 821- 826.
• 4: H.H. Chao et al., 'Designing the Micra/370," IEEE Design & Test, June 1987, pp. 32-40.
• 5: P. Galsinger, "Design and Test of the 80386," IEEE Design & Test, June 1987, pp. 42-50.
• 6: S.M. Thatte and J.A. Abraham, "Test generation for microprocessors," IEEE Trans. Computers, C-29, No. 6, June 1980, pp. 429-441.
• 7: D. Brahme and J. A. Abraham, "Functional testing of microprocessors,' IEEE Trans. Computers, June 1984, pp. 475- 485.
• 8: Sunil K. Jain , Alfred K. Susskind, Test strategy for microprocessers, Proceedings of the 20th conference on Design automation, p.703-708, June 27-29, 1983, Miami Beach, Florida, United States
• 9: Stephen Y.H. Su , Tonysheng Lin, Functional testing techniques for digital LSI/VLSI systems, Proceedings of the 21st conference on Design automation, p.517-528, June 25-27, 1984, Albuquerque, New Mexico, United States
• 10: John Mick , James Brick, Bit-Slice Microprocessor Design, McGraw-Hill, Inc., New York, NY, 1980
• 11: AM29300 Family Handbook, AMD, 1985.
• 12: 32-bit CMOS Processor 13uilding Blocks, Tl, 1988.
• 13: Christos A. Papachristou, Hardware microcontrol schemes using PLAs, Proceedings of the 14th annual workshop on Microprogramming, p.3-16, December 01-01, 1981, Chatham, Massachusetts, United States
• 14: Francois Anceau, The architecture of microprocessors, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1987
• 15: Y.K. Malaiya, "The case of the missing nanoROM,' in preparation.
• 16: Skip Stritter , Nick Tredennick, Microprogrammed implementation of a single chip microprocessor, Proceedings of the 11th annual workshop on Microprogramming, p.8-16, November 19-22, 1978, Pacific Grove, California, United States
• 17: Glen G. Langdon, Jr., Computer Design, Computeach Press, Incorporated, 1982
• 18: Y. K. Malaiya , S. Feng, Design of a testable RISC-to-CISC control architecture, Proceedings of the 21st annual workshop on Microprogramming and microarchitecture, p.57-59, November 28-December 02, 1988, San Diego, California, United States
• 19: Y.K. Malaiya, "A generalized representation of microprogrammed control,' Technical Report, 1988.
• 20: T. Sridhar and SM. Thatte, "Concurrent checking of program flow in VLSl processors,' Proc ITC, Oct. 1982, pp. 191-199.
• 21: S.V. Iyengar and L.L. Kinney, "Concurrent testing of flow of control in simple microprogrammed control units.
• 22: Y.K. Malaiya, B. Gupta, A.P. Jayasumana, M. Sankaran and S. Yang, "Functional fault modeling for elementary st(atic storage elements," 12th Annual IEEE Design For Testability Workshop, April 1989.
• 23: T. Chakraborty and S. Ghosh, "On behavior fault modeling for combinational digital designs," Proc. ITC, Sept. 1988, pp. 593-600.
• 24: M.A. Breuer and A.D. Friedman, "Diagnosis and reliable design of digital systems," Computer Science Press, 1976j pp. 5659.
• 25: Y.K. Malaiya and S. Yang, "The coverage problem for random testing," Proc. ITC, Oct. 1984, pp. 237-245.
• 26: Y.K. Malaiya, "Options in control implementations," Proc. IEEE Int. Conf. on Computer Design, Oct. 1985, pp. 267-272.
• 27: J.P. Hays, "Detection of pattern sensitive faults in random-access memories," IEEE Trans. Computers, Feb. 1975, pp. 150-157.
• 28: V.D. Agrawal, "An information theoretic approach to digital fault testing," IEEE Trans. Computers, August 1981, pp. 582-587.
• 29: C.E. Shannon, "A mathematical theory of communication," Bell Syst . Tech. Journal, July 1948, pp. 379-423.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.1 CONTROL STRUCTURES AND MICROPROGRAMMING

Additional Classification:
  B. Hardware
  B.1 CONTROL STRUCTURES AND MICROPROGRAMMING
      B.1.5 Microcode Applications
          Subjects: Firmware support of operating systems/instruction sets**

  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.3 Microcomputers
          Subjects: Microprocessors

General Terms:
Design, Performance, Theory