Locating functional errors in logic circuits

ABSTRACT

In the verification phase of the design of logic circuits using the top-down approach, it is necessary not only to detect but also to locate the source of any inconsistencies that may exist between the functional-level description and its gate-level implementation. In this paper we present a method that determines the areas, within the gate-level circuit, that contain the functional errors. The indicated areas are shown to have sufficient resolution to allow the designer to quickly find the cause of the inconsistency and, therefore, reduce the time required for debugging.

REFERENCES

• ABAD88: M. S. A badir, J. Ferguson, T. E. Kirkland, "Logic Design Verification Via Test Generation," IEEE Trans. Computer-Aided Design, vol. 7, no. 1, pp. 138-148, Jan. 1988.
• AKER80: S. B. Akers, "A Procedure for Functional Design Verification," Proc. l Oth International Symposium on Fault- Toleran~ Computing, pp. 65-67, 1980.
• BARR84: Harry G. Barrow, VERIFY: a program for proving correctness of digital hardware designs, Artificial Intelligence, v.24 n.1-3, p.437-491, Dec. 1984 [doi>10.1016/0004-3702(84)90044-4]
• BRYA86: Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
• CHU65: Yaohan Chu, An ALGOL-like computer design language, Communications of the ACM, v.8 n.10, p.607-615, Oct. 1965 [doi>10.1145/365628.365650]
• DALE68: J. R. Duley and D. L. Dietmeyer, "A Digital System Design Language (DDL)," IEEE Trans. Computers, vol. C-17, no. 97 pp. 850-861, Sept. 1968.
• GARE79: Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
• HACH88: G. D. Hachtel and R. M. Jacoby, "Verification Algorithms for VLSI Synthesis," IEEE Trans. CompuSer-Aided Design, vol. 7, no. 5, pp. 616--640, May 1988.
• KATO83: S. Kato and T. Sasaki, "FDL: A Structural Behavior Description Language," CHDL 83, pp. 137-152, 1983.
• ODAW86: Gotaro Odawara , Masahiro Tomita , Osamu Okuzawa , Tomomichi Ohta , Zhen-quan Zhuang, A logic verifier based on Boolean comparison, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.208-214, July 1986, Las Vegas, Nevada, United States
• SASA84: T. Sasaki, S. Kato, N. Nomizu, and H. Tanaka, "Logic Design Verification Using Automated Test Generation," Proc. 198,~ International Test Con}erence, pp. 88-94, 1984.
• SMIT82: G. L. Smith, R. J. Bahnsen, and H. Halliwell, "Boolean Comparison of Hardware and Flowcharts," IBM J. Res. Dev., vol. 26, no. 1, pp. 106-116, Jan. 1982.
• SRIN88: N. C. Srinivas and V. D. Agrawal, "Formal Verification of Digital Circuits Using Hybrid Simulation," IEEE Circuits Device Mag., pp. 19--27, Jan. 1988.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Automatic synthesis
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Verification

General Terms:
Algorithms, Design, Verification