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ORCA a sea-of-gates place and route system
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 26th ACM/IEEE Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 122 - 127  
Year of Publication: 1989
ISBN:0-89791-310-8
Authors
M. Igusa  Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California
M. Beardslee  Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California
A. Sangiovanni-Vicentelli  Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\TCDA : TC Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 17,   Citation Count: 5
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ABSTRACT

Sea-of-gates is becoming an important design style for Application Specific Integrated Circuits (ASICs). The sea-of-gates technology offers more flexible placement and routing options not available in gate arrays. Very few systems are available today that can automatically layout sea-of-gates and none of these systems effectively use the features available in sea-of-gates architecture. ORCA is a place and route system for sea-of-gates, whose objective is to produce the highest density layout by fully exploiting the inherent features of this new design style. The ORCA system starts with a module generator which preprocesses memory arrays and other logic with a regular structure to form high density macros. The remaining logic is clustered together to form flexible macros, which we call porous. The porous macro-cells allow global routing to pass through the macro instead of detouring around its perimeter. The porous macros are dynamically shaped and resized by interaction with global wiring analysis. Finally, a general channelless area router has been developed to address the multiple layers of interconnect and routing areas which will be dominantly over-the-cell. Due to the large size of the problem (e.g. 100,000 gates), the placement and routing algorithms are hierarchical.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
A. Hui et al. A 4.1k gates double metal hcmos sea of gates array. Proc. IEEE CICC, : 15-17, May 1985.
 
2
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Ravi Nair. A simple yet effective technique for global wiring. IEEE Trans. on Computer-Aided Design, CAD-6:165-172, 1987.
 
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M. Burstein and R. Pelavin. Hierarchical wire routing. IEEE Trans. on Computer-Aided Design, CAD-2:223-234, 1983.
 
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11
D. Harrison et al. Data management and graphics editing in the Berkeley design environment. Proc. ICCAD, Nov 1986.


Collaborative Colleagues:
M. Igusa: colleagues
M. Beardslee: colleagues
A. Sangiovanni-Vicentelli: colleagues

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