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Data dependency graph bracing
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Source International Symposium on Microarchitecture archive
Proceedings of the 21st annual workshop on Microprogramming and microarchitecture table of contents
San Diego, California, United States
Pages: 91 - 93  
Year of Publication: 1988
ISBN:0-8186-1919-8
Author
V. H. Allan  Department of Computer Science, Utah State University
Sponsor
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 8,   Citation Count: 1
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ABSTRACT

The Sunburst compiler refined at Utah State University employs a powerful mechanism for management of data anti-dependencies in data dependency graphs, DDG's: the DDG Bracer. The term bracing1 is used to mean the fastening of two or more parts together. There are two major goals in bracing: 1) semantic correctness, and 2) creation of an optimal DDG. Bracing provides necessary joining of code fragments, produced by a divide and conquer code generation algorithm, while yielding multiple code sequences. Since no anti-dependency arcs are present, the input DDG's are said to be in normal form. Because anti-dependency arcs occur only when a resource must be reused, a DDG in normal form represents infinite resources. The output DDG is a merging of the two input DDG's such that data dependency arcs between the two DDG's are inserted and data anti-dependency arcs are added to sequentialize the use of common resources. Vegdahl [Veg82] was one of the first to recognize the importance of live track manipulation. A live track is an ordered pair: the first component is the microoperation node ( MO) in which a resource is born, and the second component is the set of nodes in which the resource dies.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
All86
 
MS86
R.A. Mueller and P.H. Sweany. Horizon Code Generator Series-Parallel DDG Coupler/Decoupler (Version s.1). Technical Report MAD-86-10, Firmware Engineering and Micro-Architecture Design Laboratory, Colorado State University, Fort Collins, CO, August 1986.
 
Veg82



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