Efficient macro-code emulation in hardwired pipelined processors

ABSTRACT

Traditionally microcoded computers have been the ideal machines for implementing scalable architectures. These machines easily implement application-specific functionality in microcode and they allow architecturally transparent variation of cost/performance by trading off application code, microcode, and hardware. In contrast, hardwired machines are intrinsically incapable of implementing scalability, because they only implement a single level of interpretation. Recent RISC designs have introduced architectural features which partly resolve the scalability issues. They implement architectural openendness to allow application-specific functionality to be added to the architecture (by means of coprocessors and special function units). Additionally they define functions which, depending on application, cost, and performance, can be implemented in hardware or, by means of emulation, in software. Although identical from an abstract point of view, scalability by means of microprogramming and by means of emulation on a hardwired machine is significantly different. This paper describes the emulation facility provided in SCARCE (SCalable ARChitecture Experiment), a streamlined architecture specifically designed for a wide range of embedded applications, requiring high performance. While architecturally transparent, this emulation facility operates with little overhead (8 cycles), adds three control registers, and is always interruptible. By increasing the hardware investment, the overhead could be decreased to 4 cycles per trap.

REFERENCES

• 1: M.J. Mahon, R.B. Lee, T.C. Miller, J.C. Huck, and W.R. Bryg. Hewlett-Packard precision architecture: the processor. Hewlett-Packard Journal, 37:4-21, August 1986.
• 2: Motorola Inc. MC88104 32-bit Third Generation RISC Microprocessor, Technical Summary. 1988.
• 3: Fairchild. Introduction to thtr CLIPPER architecture. Fairchild, 1986.
• 4: Advanced Micro Devices. Am29000 U7ser'd Manual. February 1987.
• 5: Emmanuel-Manolis George Katevenis, Reduced instruction set computer architectures for vlsi (microprocessor, risc, multiple-windows - of - registers), 1983
• 6: G. S. Taylor , P. N. Hilfinger , J. R. Larus , D. A. Patterson , B. G. Zorn, Evaluation of the SPUR Lisp architecture, Proceedings of the 13th annual international symposium on Computer architecture, p.444-452, June 02-05, 1986, Tokyo, Japan
• 7: Michael J. Flynn , Chad L. Mitchell , Johannes M. Mulder, And now a case for more complex instruction sets, Computer, v.20 n.9, p.71-83, Sept. 1987 [doi>10.1109/MC.1987.1663696]
• 8: P. Chow , M. Horowitz, Architectural tradeoffs in the design of MIPS-X, Proceedings of the 14th annual international symposium on Computer architecture, p.300-308, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30384]
• 9: R. H. Halstead, Jr. , T. Fujita, MASA: a multithreaded processor architecture for parallel symbolic computing, Proceedings of the 15th Annual International Symposium on Computer architecture, p.443-451, May 30-June 02, 1988, Honolulu, Hawaii, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.1 CONTROL STRUCTURES AND MICROPROGRAMMING
      B.1.1 Control Design Styles
          Subjects: Hardwired control**

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Pipeline processors**

General Terms:
Algorithms, Design, Performance