Path delay fault testing using test points

ABSTRACT

Inserting controllable/observable points in the test architecture has been shown to be a viable method for reducing the number of path delay faults that need to be tested in a circuit. In order to have a minimal impact on the operation clock and more accuracy in testing, it is proposed that test points should be inserted with the additional constraint that every path has a bounded number of test points. A polynomial time solvable integer linear programming (ILP) formulation serves as the basis for the presented test placement methodology. Due to the ILP's global optimization property we achieve results that are comparable to those by an existing greedy technique for the less constrained test point placement problem.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

  E. Data
  E.1 DATA STRUCTURES
      Subjects: Graphs and networks

  G. Mathematics of Computing
  G.2 DISCRETE MATHEMATICS
      G.2.2 Graph Theory
          Subjects: Graph algorithms; Path and circuit problems

  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Algorithms, Performance, Reliability

Keywords:
Automatic test pattern generation, delay testing, design for testability, path delay fault simulation (coverage), path delay fault testing, testing digital circuits