Scheduler-based DRAM energy management

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Scheduler-based DRAM energy management

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 39th annual Design Automation Conference table of contents

New Orleans, Louisiana, USA

SESSION: Scheduling techniques for embedded systems table of contents

Pages: 697 - 702

Year of Publication: 2002

ISBN ~ ISSN:0738-100X , 1-58113-461-4

Authors

V. Delaluz	The Pennsylvania State University, University Park, PA
A. Sivasubramaniam	The Pennsylvania State University, University Park, PA
M. Kandemir	The Pennsylvania State University, University Park, PA
N. Vijaykrishnan	The Pennsylvania State University, University Park, PA
M. J. Irwin	The Pennsylvania State University, University Park, PA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 34, Citation Count: 23

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abstract references cited by index terms collaborative colleagues peer to peer

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ABSTRACT

Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operating modes. While hardware-based techniques require extra logic to keep track of memory references and make decisions about future mode transitions, compiler-directed schemes can only work on a single application at a time and demand sophisticated program analysis support. In this work, we present an operating system (OS) based solution where the OS scheduler directs the power mode transitions by keeping track of module accesses for each process in the system. This global view combined with the flexibility of a software approach brings large energy savings at no extra hardware cost. Our implementation using a full-fledged OS shows that the proposed technique is also very robust when different system and workload parameters are modified, and provides the first set of experimental results for memory energy optimization with a multiprogrammed workload on a real platform. The proposed technique is applicable to both embedded systems and high-end computing platforms.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 24

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	Chanik Park , Jeong-Uk Kang , Seon-Yeong Park , Jin-Soo Kim, Energy-aware demand paging on NAND flash-based embedded storages, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Song Liu , Seda Ogrenci Memik , Yu Zhang , Gokhan Memik, A power and temperature aware DRAM architecture, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Jung-hi Min , Hojung Cha, Reducing display power in DVS-enabled handheld systems, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Hai Huang , Kang G. Shin , Charles Lefurgy , Tom Keller, Improving energy efficiency by making DRAM less randomly accessed, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Hai Huang , Padmanabhan Pillai , Kang G. Shin, Design and implementation of power-aware virtual memory, Proceedings of the USENIX Annual Technical Conference 2003 on USENIX Annual Technical Conference, p.5-5, June 09-14, 2003, San Antonio, Texas
	Hongzhong Zheng , Jiang Lin , Zhao Zhang , Eugene Gorbatov , Howard David , Zhichun Zhu, Mini-rank: Adaptive DRAM architecture for improving memory power efficiency, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.210-221, November 08-12, 2008
	Ravi K. Venkatesan , Ahmed S. Al-Zawawi , Krishnan Sivasubramanian , Eric Rotenberg, ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling, IEEE Transactions on Computers, v.56 n.2, p.147-160, February 2007
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	Anand Ramachandran , Margarida F. Jacome, Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Radoslaw Szymanek , Francky Catthoor , Krzysztof Kuchcinski, Time-Energy Design Space Exploration for Multi-Layer Memory Architectures, Proceedings of the conference on Design, automation and test in Europe, p.10318, February 16-20, 2004
	Charles Lefurgy , Karthick Rajamani , Freeman Rawson , Wes Felter , Michael Kistler , Tom W. Keller, Energy Management for Commercial Servers, Computer, v.36 n.12, p.39-48, December 2003
	Jung-Hi Min , Hojung Cha , Vason P. Srini, Dynamic power management of DRAM using accessed physical addresses, Microprocessors & Microsystems, v.31 n.1, p.15-24, February, 2007
	Zhong Wang , Xiaobo Sharon Hu, Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks, Proceedings of the conference on Design, automation and test in Europe, p.10312, February 16-20, 2004
	Peng Rong , Massoud Pedram, Hierarchical power management with application to scheduling, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Dongwook Lee , Sungjoo Yoo , Kiyoung Choi, Entry control in network-on-chip for memory power reduction, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Vincent W. Freeh , David K. Lowenthal , Feng Pan , Nandini Kappiah , Rob Springer , Barry L. Rountree , Mark E. Femal, Analyzing the Energy-Time Trade-Off in High-Performance Computing Applications, IEEE Transactions on Parallel and Distributed Systems, v.18 n.6, p.835-848, June 2007
	Y. C. Tay , Min Zou, A page fault equation for modeling the effect of memory size, Performance Evaluation, v.63 n.2, p.99-130, February 2006
	Xiaodong Li , Ritu Gupta , Sarita V. Adve , Yuanyuan Zhou, Cross-component energy management: Joint adaptation of processor and memory, ACM Transactions on Architecture and Code Optimization (TACO), v.4 n.3, p.14-es, September 2007
	Vincent W. Freeh , David K. Lowenthal, Using multiple energy gears in MPI programs on a power-scalable cluster, Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming, June 15-17, 2005, Chicago, IL, USA
	Pin Zhou , Vivek Pandey , Jagadeesan Sundaresan , Anand Raghuraman , Yuanyuan Zhou , Sanjeev Kumar, Dynamic tracking of page miss ratio curve for memory management, ACM SIGOPS Operating Systems Review, v.38 n.5, December 2004
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	Jung-Hi Min , Hojung Cha , Rhan Ha, System-level integrated power management for handheld systems, Microprocessors & Microsystems, v.33 n.3, p.201-210, May, 2009