Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter

ABSTRACT

The systematic design of a high-speed, high-accuracy Nyquist-rate A/D converter is proposed. The presented design methodology covers the complete flow and is supported by software tools. A generic behavioral model is used to explore the A/D converter's specifications during high-level design and exploration. The inputs to the flow are the specifications of the A/D converter and the technology process. The result is a generated layout and the corresponding extracted behavioral model. The approach has been applied to a real-life test case, where a Nyquist-rate 8-bit 200 MS/s 4-2 interpolating/averaging A/D converter was developed for a WLAN application.

REFERENCES

• 1: G. Van der Plas, J. Vandenbussche, et.al., "Statistical Behavioral Modeling for A/D Converters", Proc. on the IEEE 1999 ICECS, pp. 1713--1716, Cyprus, Sept. 1999.
• 2: G.Gielen and R. Rutenbar, Computer-Aided Design of Analog and Mixed-signal Integrated Circuits, Proc. IEEE, vol. 88, no. 12, pp. 1825--1852, Dec. 2000.
• 3: R. Van de Plassche, Integrated Analog-To-Digital and Digital-To-Analog Converters, Kluwer Academic Publishers, ISBN 0-7923--9436-4, p. 193--204, 1994.
• 4: K. Bult, A. Buchwald, Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1 mm2", IEEE JSSC, Vol. 32, No. 12, December, 1997, p. 1887--1895.
• 5: E. Liu, et.al. A behavioral representation for Nyquist Rate A/D Converters, in Proc. IEEE International Conference on Computer-Aided Design, 1991, pp. 386--389.
• 6: T.L.Brooks, et. al., A 16b Sigma-Delta Pipeline ADC with 2.5MHz Output Data-rate, in Proc. ISSCC, Feb 1997, p 404.
• 7: A. Venes et. al., An 80 MHz, 80 mW, 8 bit CMOS Folding A/D Converter with Distributed Track and Hold Preprocessing, IEEE JSSC, vol. 31, no. 12, Dec. 1996.
• 8: G. Gielen, H. Walscharts and W. Sansen, ISAAC: a symbolic simulator for analog integrated circuits, IEEE JSSC, vol.24, no. 6, December 1989, pp. 1587--1597.
• 9: Geert Van der Plas, et.al., "Symbolic Analysis of CMOS Regenerative Comparators", European Conference on Circuit Theory and Design, pp. 86--89, Italy, August 1999.
• 10: K. Uyttenhove, A. Marques and M. Steyaert , A6-bit, 1GHz Acquisition Speed ADC in 0.35 CMOS", in Proc. IEEE CICC, May 2000, Orlando, Florida, pp 249--252.
• 11: This product includes software developed by Lester Ingber and other contributors: http://www.ingber.com/
• 12: K. Lampaert, G. Gielen and W. Sansen, A Performance-Driven Placement Tool for Analog Integrated Circuits, IEEE JSSC, pp. 773--781, July 1995.
• 13: G. Van der Plas, J. Vandenbussche, et. al., "Mondriaan: a Tool for Automated Layout Synthesis of Array-type Analog Blocks", in Proc. IEEE CICC, pp. 485--488, May 1998.
• 14: W. Verhaegen , G. Van der Plas , G. Gielen, Automated test pattern generation for analog integrated circuits, Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), p.296, April 27-May 01, 1997

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.m Miscellaneous

General Terms:
Design

Keywords:
A/D converters, flash, interpolating, simulated annealing