Prefetching for improved bus wrapper performance in cores

ABSTRACT

Reuse of cores can reduce design time for systems-on-a-chip. Such reuse is dependent on being able to easily interface a core to any bus. To enable such interfacing, many propose separating a core's interface from its internals by using a bus wrapper. However, this separation can lead to a performance penalty when reading a core's internal registers. In this paper, we introduce prefetching, which is analogous to caching, as a technique to reduce or eliminate this performance penalty, involving a tradeoff with power and size. We describe the prefetching technique, classify different types of registers, describe our initial prefetching architectures and heuristics for certain classes of registers, and highlight experiments demonstrating the performance improvements and size/power tradeoffs. We further introduce a technique for automatically designing a prefetch unit that satisfies user-imposed register-access constraints. The technique benefits from mapping the prefetching problem to the well-known real-time process scheduling problem. We then extend the technique to allow user-specified register interdependencies, using a Petri net model, resulting in even more efficient prefetch schedules.

REFERENCES

• 1: Alan Burns , A. J. Wellings, Real-time systems and their programming languages, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1990
• 2: Pai Chou , Ross B. Ortega , Gaetano Borriello, Interface co-synthesis techniques for embedded systems, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.280-287, November 05-09, 1995, San Jose, California, United States
• 3: Benoit Clement , Richard Hersemeule , Etienne Lantreibecq , Bernard Ramanadin , Pierre Coulomb , Francois Pogodalla, Fast prototyping: a system design flow applied to a complex system-on-chip multiprocessor design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.420-424, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309971]
• 4: COWARE. 1999. CoWare N2C design system overview. http://www.coware.com/ products.html.
• 5: Josef Fleischmann , Klaus Buchenrieder , Rainer Kress, Java driven codesign and prototyping of networked embedded systems, Proceedings of the 36th ACM/IEEE conference on Design automation, p.794-797, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310068]
• 6: Michael Gasteier , Manfred Glesner, Bus-Based Communication Synthesis on System-Level, Proceedings of the 9th international symposium on System synthesis, p.65, November 06-08, 1996
• 7: Christoforos E. Kozyrakis , David A. Patterson, A New Direction for Computer Architecture Research, Computer, v.31 n.11, p.24-32, November 1998 [doi>10.1109/2.730733]
• 8: KUHN, T., ROSENSTIEL, W., AND KEBSCHULL, U. 1997. Description and simulation of hardware/software systems with Java. In Design Automation Conference (1997).
• 9: C. L. Liu , James W. Layland, Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment, Journal of the ACM (JACM), v.20 n.1, p.46-61, Jan. 1973 [doi>10.1145/321738.321743]
• 10: Vijay K. Madisetti , Lan Shen, Interface Design for Core-Based Systems, IEEE Design & Test, v.14 n.4, p.42-51, October 1997 [doi>10.1109/54.632880]
• 11: MENTOR GRAPHICS. n.d. Inventra core library. http://www.mentorg.com/inventra/.
• 12: METAFLOW. 1999. Implosion ARM-based Internet appliance system on a chip platform. http://www.metaflow.com/ html/ implosion.htm.
• 13: MOTOROLA. 1999. IP interface standard document. http://www.mot-sps.com/ technology/srs/.
• 14: David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
• 15: PHILIPS SEMICONDUCTORS. 1999. Introduction to rapid silicon prototyping: hardware-software co-design for embedded systems-on-a-chip ICs. http://www.semiconductors.com/ acrobat/other/ technology/velocity/paper2221.pdf.
• 16: RABAEY, J., ABNOUS, A., ICHIKAWA, Y., SENO, K., AND WAN, M. 1997. Heterogeneous reconfigurable systems. In Proceedings of the IEEE Workshop on Design and Implementation of Signal Processing Systems (1997), 24-34.
• 17: James A. Rowson , Alberto Sangiovanni-Vincentelli, Interface-based design, Proceedings of the 34th annual conference on Design automation, p.178-183, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266060]
• 18: SEMICONDUCTOR INDUSTRY ASSOCIATION. 1999. International technology roadmap for semiconductors: 1999 edition. International SEMATECH, Austin, TX.
• 19: Frank Vahid , Tony Givargis, The case for a configure-and-execute paradigm, Proceedings of the seventh international workshop on Hardware/software codesign, p.59-63, March 1999, Rome, Italy [doi>10.1145/301177.301211]
• 20: Frank Vahid , Linus Tauro, An Object-Oriented Communication Library for Hardware-Software CoDesign, Proceedings of the 5th International Workshop on Hardware/Software Co-Design, p.81, March 24-26, 1997
• 21: VAN MEERBERGEN, J., TIMMER, A., LEIJTEN, J., HARMSZE, F., AND STRIK, M. 1998. Experiences with system level design for consumer ICs. In Proceedings of the IEEE Computer Society Workshop on VLSI System Level Design (1998).
• 22: Steven Vercauteren , Bill Lin , Hugo De Man, Constructing application-specific heterogeneous embedded architectures from custom HW/SW applications, Proceedings of the 33rd annual conference on Design automation, p.521-526, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240617]
• 23: VIRTUAL SOCKET INTERFACE ASSOCIATION. 1997a. Architecture document. http://www.vsi.org.
• 24: VIRTUAL SOCKET INTERFACE ASSOCIATION. 1997b. Virtual component interface standard version 1.0. http://www.vsi.org.
• 25: VIRTUAL SOCKET INTERFACE ASSOCIATION. 1998. On-chip bus development working group, Specification 1 Version 1.0 (OCB 1 1.0). http://www.vsi.org.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Interfaces

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.0 General

  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.4 VLSI Systems

General Terms:
Design, Performance

Keywords:
Bus wrapper, PVCI, VSIA, cores, design reuse, intellectual property, interfacing, on-chip bus, system-on-a-chip