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Cached-code compression for energy minimization in embedded processors
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 2001 international symposium on Low power electronics and design table of contents
Huntington Beach, California, United States
Pages: 322 - 327  
Year of Publication: 2001
ISBN:1-58113-371-5
Authors
Luca Benini  Università di Bologna, Bologna, Italy 40136
Alberto Macii  Politecnico di Torino, Torino, Italy 10129
Alberto Nannarelli  Università di Roma Tor Vergata, Roma, Italy 00133
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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S. Y. Liao, S. Devadas, K. Keutzer, "Code Density Optimization for Embedded DSP Processors Using Data Compression Techniques," IEEE Trans. on CAD, Vol. 17, No. 7, pp. 601-608, 1998.
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J. Davis II et al., Overview of the Ptolemy Project, UCB/ERL Tech. Report No. M99/37, UC Berkeley, 1999.
 
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C. Moura, SuperDLX: A Generic Superscalar Simulator, ACAPS Technical Memo 64, McGill Univ., 1993.

CITED BY  12
 
 
 
 
 

Collaborative Colleagues:
Luca Benini: colleagues
Alberto Macii: colleagues
Alberto Nannarelli: colleagues

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