Automatic performance setting for dynamic voltage scaling

ABSTRACT

The emphasis on processors that are both low power and high performance has resulted in the incorporation of dynamic voltage scaling into processor designs. This feature allows one to make fine granularity trade-offs between power use and performance, provided there is a mechanism in the OS to control that trade-off. In this paper, we describe a novel software approach to automatically controlling dynamic voltage scaling in order to optimize energy use. Our mechanism is implemented in the Linux kernel and requires no modification of user programs. Unlike previous automated approaches, our method works equally well with irregular and multiprogrammed workloads. Moreover, it has the ability to ensure that the quality of interactive performance is within user specified parameters. Our experiments show that as a result of our algorithm, processor energy savings of as much as 75% can be achieved with only a minimal impact on the user experience.

REFERENCES

• 1: Stuart K. Card , Allen Newell , Thomas P. Moran, The Psychology of Human-Computer Interaction, Lawrence Erlbaum Associates, Inc., Mahwah, NJ, 1983
• 2: Developer manual: "Intel 80200 Processor Based on Intel XScale Microarchitecture" http://developer.intel.com/design/ iio/manuals/273411.htm
• 3: Kristián Flautner , Rich Uhlig , Steve Reinhardt , Trevor Mudge, Thread-level parallelism and interactive performance of desktop applications, Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, p.129-138, November 2000, Cambridge, Massachusetts, United States
• 4: Jason Flinn , M. Satyanarayanan, Energy-aware adaptation for mobile applications, Proceedings of the seventeenth ACM symposium on Operating systems principles, p.48-63, December 12-15, 1999, Charleston, South Carolina, United States
• 5: Kinshuk Govil , Edwin Chan , Hal Wasserman, Comparing algorithm for dynamic speed-setting of a low-power CPU, Proceedings of the 1st annual international conference on Mobile computing and networking, p.13-25, November 13-15, 1995, Berkeley, California, United States [doi>10.1145/215530.215546]
• 6: D. Grunwald, P. Levis, K. Farkas, C. B. Morrey III, and M. Neufeld. Policies for Dynamic Clock Scheduling. Proceedings of the Fourth Symposium on Operating Systems Design & Implementation, October 2000.
• 7: C. M. Krishna , Yann-Hang Lee, Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems, Proceedings of the Sixth IEEE Real Time Technology and Applications Symposium (RTAS 2000), p.156, May 31-June 02, 2000
• 8: D. Laird, Crusoe Processor Products and Technology http:// www.transmeta.com/press/download/pdf/laird.pdf, January 2000.
• 9: Trevor N. Mudge, Power: A First Class Design Constraint for Future Architecture and Automation, Proceedings of the 7th International Conference on High Performance Computing, p.215-224, December 17-20, 2000
• 10: Takanori Okuma , Tohru Ishihara , Hiroto Yasuura, Real-Time Task Scheduling for a Variable Voltage Processor, Proceedings of the 12th international symposium on System synthesis, p.24, November 01-04, 1999
• 11: Dan R. Olsen, Jr., Developing user interfaces, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1998
• 12: Trevor Pering , Tom Burd , Robert Brodersen, The simulation and evaluation of dynamic voltage scaling algorithms, Proceedings of the 1998 international symposium on Low power electronics and design, p.76-81, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280790]
• 13: Trevor Pering , Thomas Burd , Robert Brodersen, Voltage scheduling in the IpARM microprocessor system, Proceedings of the 2000 international symposium on Low power electronics and design, p.96-101, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344530]
• 14: Youngsoo Shin , Kiyoung Choi, Power conscious fixed priority scheduling for hard real-time systems, Proceedings of the 36th ACM/IEEE conference on Design automation, p.134-139, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309901]
• 15: M. Weiser, B. Welch, A. Demers, and S. Shenker. Scheduling for Reduced CPU Energy. Proceedings of the First Symposium of Operating Systems Design and Implementation, November 1994.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.3 Microcomputers
          Subjects: Microprocessors

Additional Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Performance attributes

  I. Computing Methodologies
  I.5 PATTERN RECOGNITION
      I.5.4 Applications
          Subjects: Signal processing

General Terms:
Design, Experimentation, Performance