An automated design of minimum-area IC power/ground nets

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

An automated design of minimum-area IC power/ground nets

Full text

Pdf (823 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents

Miami Beach, Florida, United States

Pages: 223 - 229

Year of Publication: 1987

ISBN:0-8186-0781-5

Author

S. Chowdhury

Department of Electrical & Computer Engineering, The University of Iowa, Iowa City, IA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 11, Citation Count: 8

Additional Information:

abstract references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/37888.37927 What is a DOI?

ABSTRACT

Given tree topologies for routing power/ground (p/g) nets in integrated circuits, this paper formulates and solves the problem of determining the widths of the branches of the trees. Constraints are developed in order to maintain proper logic levels and switching speed, to prevent electromigration, and to satisfy certain design rule and regularity requirements. The area required by the p/g distribution system is minimized subject to these constraints. Some case studies are also presented.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M.S. Bazaraa and C.M. Shetty, Nonlinear Programming, John Wiley & Sons, 1979.
	2	J. R. Black, "Electromigration failure modes in aluminium metalization for semiconductor devices," Proc. IEEE, vol. 57, pp. 1587-1594, Sept., 1969.
	3	S. Chowdhury , M. A. Breuer, The construction of minimal area power and ground nets for VLSI circuits, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.794-797, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317996]
	4	S. Chowdhury , M. A. Breuer, Minimal area sizing of power and ground nets for VLSI circuits, Proceedings of the fourth MIT conference on Advanced research in VLSI, p.141-169, June 1986, Cambridge, Massachusetts, United States
	5	F.M. D'Heurle, "Electromigration and failure in electronics: An introduction," Proc. IEEE, vol. 597 no. 10, pp. 1409-1418~ October, 1971.
	6	Carver Mead , Lynn Conway, Introduction to VLSI Systems, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1979
	7	Anderew S. Moulton, Laying the power and ground wires on a VLSI chip, Proceedings of the 20th conference on Design automation, p.754-755, June 27-29, 1983, Miami Beach, Florida, United States
	8	Bryan T. Preas , Patrick G. Karger, Automatic placement a review of current techniques (tutorial session), Proceedings of the 23rd ACM/IEEE conference on Design automation, p.622-629, July 1986, Las Vegas, Nevada, United States
	9	H-J. Rothermel , D. A. Mlynski, Computation of power supply nets in VLSI layout, Proceedings of the 18th conference on Design automation, p.37-42, June 29-July 01, 1981, Nashville, Tennessee, United States
	10	W.S. Song and L.A. Glosser, "Power distribution techniques for VLSI circuits," Journal of Solid State Circuits, Feb., 1986.
	11	Z.A. Syed and A. El Gamal, "Single layer routing of power and ground networks in integrated circuits," Journal of Digital Systems, vol. 6, no. 1, pp. 53-63, 1982.
	12	D.M. Topkis and A.F. Veinott, "On the convergence of some feasible direction algorithms for nonlinear programming," SIAM J. Control, 5, pp. 268- 279, 1967.
	13	G. Zoutendijk, "Methods of feasible directions," Elsevier, Amsterdam, 1960.

CITED BY 8

	H. Cai, Multi-pads, single layer power net routing in VLSI circuits, Proceedings of the 25th ACM/IEEE conference on Design automation, p.183-188, June 12-15, 1988, Atlantic City, New Jersey, United States
	Thorsten Adler , Erich Barke, Single step current driven routing of multiterminal signal nets for analog applications, Proceedings of the conference on Design, automation and test in Europe, p.446-450, March 27-30, 2000, Paris, France
	Thorsten Adler , Hiltrud Brocke , Lars Hedrich , Erich Barke, A current driven routing and verification methodology for analog applications, Proceedings of the 37th conference on Design automation, p.385-389, June 05-09, 2000, Los Angeles, California, United States
	R. Dutta , M. Marek-Sadowska, Automatic sizing of power/ground (P/G) networks in VLSI, Proceedings of the 26th ACM/IEEE conference on Design automation, p.783-786, June 25-28, 1989, Las Vegas, Nevada, United States
	Reiner Kolla, A dynamic programming approach to the power supply net sizing problem, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	Jens Lienig , Goeran Jerke , Thorsten Adler, Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.372, January 07-11, 2002
	Don Stark , Mark Horowitz, Analyzing CMOS power supply networks using Ariel, Proceedings of the 25th ACM/IEEE conference on Design automation, p.460-464, June 12-15, 1988, Atlantic City, New Jersey, United States
	Jens Lienig , Göran Jerke, Current-driven wire planning for electromigration avoidance in analog circuits, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan