ACM Home Page
Please provide us with feedback. Feedback
REAL: a program for REgister ALlocation
Full text PdfPdf (467 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents
Miami Beach, Florida, United States
Pages: 210 - 215  
Year of Publication: 1987
ISBN:0-8186-0781-5
Authors
F. J. Kurdahi  Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
A. C. Parker  Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 19,   Citation Count: 68
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues   peer to peer  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/37888.37920
What is a DOI?

ABSTRACT

This paper describes the REAL REgister ALlocation program. REAL uses a track assignment algorithm taken from channel routing called the Left Edge algorithm. REAL is optimal for non-pipelined designs with no conditional branches. It is thought that REAL is also optimal for designs with conditional branches, pipelined or not. Experimental results are included in the report, which illustrate the optimal solutions found by REAL. REAL is part of the ADAM Advanced Design AutoMation system, and will be used to process designs output from MAHA and Sehwa.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
E. Girczyc and j. Knight. An Ada to Standard Cell Hardware Compiler Based on Graph Grammars and Scheduling. In Proceedings, 1984 International Con- {erence on Computer Design - IGCD, pages 726-729, October 1984.
 
3
4
 
5
N. Park and A. C. Parker. Synthesis of Optimal Pipeline Clocking Schemes. Technical Report DISC/85-1, Dept. of EE-Systems, University of Southern California, January 1985.
 
6
 
7
 
8
C.-J. Tseng and D.P. Siewiorek. Automated Synthesis of Data Paths in Digital Systems. {EEE Trans, on CAD, CAD-5(3):379-395, July 1986.

CITED BY  70
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Collaborative Colleagues:
F. J. Kurdahi: colleagues
A. C. Parker: colleagues

Peer to Peer - Readers of this Article have also read: