Faster architectural simulation through parallelism

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Faster architectural simulation through parallelism

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 24th ACM/IEEE Design Automation Conference table of contents

Miami Beach, Florida, United States

Pages: 189 - 194

Year of Publication: 1987

ISBN:0-8186-0781-5

Authors

J. W. Smith	Parallel Processing Program at the Micmelectronics and Computer Technology Corporation, Austin Texas
K. S. Smith
R. J. Smith, II

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 5, Citation Count: 6

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abstract references cited by index terms collaborative colleagues peer to peer

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ABSTRACT

Architectural simulation of complex systems is usually constrained by available computational resources. Recently, several commercial parallel processing systems have appeared with price-performance levels that make very intense simulations affordable. In this paper, we briefly review architectural simulation technology, then describe the approach used to develop a parallel architectural simulator. Performance of the parallel simulator is then experimentally characterized and analyzed. This study is one of the earliest to report measured performance of a widely-used commercial simulator, running non-trivial designs on a popular parallel computing system.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Peacock, J. K., J. W. Wong and E. (3. Manning, "Distributed Simulation Using a Network of Processors," Computer Networks 3(1) 1979, pp 44-56.
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CITED BY 6

	Larry Soule , Anoop Gupta, Parallel Distributed-Time Logic Simulation, IEEE Design & Test, v.6 n.6, p.32-48, November 1989
	L. Soule , A. Gupta, Characterization of parallelism and deadlocks in distributed digital logic simulation, Proceedings of the 26th ACM/IEEE conference on Design automation, p.81-86, June 25-28, 1989, Las Vegas, Nevada, United States
	Larry Soulé , Tom Blank, Parallel logic simulation on general purpose machines, Proceedings of the 25th ACM/IEEE conference on Design automation, p.166-171, June 12-15, 1988, Atlantic City, New Jersey, United States
	A. Bataineh , F. Özgüner, Parallel-and-vector implementation of the event-driven logic simulation algorithm on the Cray Y-MP supercomputer, Proceedings of the 1992 ACM/IEEE conference on Supercomputing, p.444-452, November 16-20, 1992, Minneapolis, Minnesota, United States
	Larry Soulé , Anoop Gupta, An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation, ACM Transactions on Modeling and Computer Simulation (TOMACS), v.1 n.4, p.308-347, Oct. 1991
	Martin Tompa, Figures of merit: the sequel, ACM SIGACT News, v.21 n.4, p.78-81, Fall 1990