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ABSTRACT
An organization for a knowledge-based analog circuit synthesis tool is described. Analog circuit topologies are represented as a hierarchy of functional blocks; a planning mechanism is introduced to translate performance specifications between levels in this circuit hierarchy. A prototype implementation, OASYS, synthesizes sized transistor schematics for simple CMOS operational amplifiers from performance specifications and process parameters, and demonstrates the workability of the approach.
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Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 10
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L.-O. Donzelle , P.-F. Dubois , B. Hennion , J. Parissis , P. Senn, A constraint based approach to automatic design of analog cells, Proceedings of the 28th conference on ACM/IEEE design automation, p.506-509, June 17-22, 1991, San Francisco, California, United States
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E. Berkcan , M. d'Abreu , W. Laughton, Analog compilation based on successive decompositions, Proceedings of the 25th ACM/IEEE conference on Design automation, p.369-375, June 12-15, 1988, Atlantic City, New Jersey, United States
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W. P. Birmingham , A. P. Gupta , D. P. Siewiorek, The MICON system for computer design, Proceedings of the 26th ACM/IEEE conference on Design automation, p.135-140, June 25-28, 1989, Las Vegas, Nevada, United States
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