Practical low-cost CPL implementations threshold logic functions

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Practical low-cost CPL implementations threshold logic functions

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Great Lakes Symposium on VLSI archive
Proceedings of the 11th Great Lakes symposium on VLSI table of contents

West Lafayette, Indiana, United States

Pages: 139 - 144

Year of Publication: 2001

ISBN:1-58113-351-0

Authors

José M. Quintana	Instituto de Microelectrónica de Sevilla (IMSE-CNM), Avda. Reina Mercedes s/n, 41012 Sevilla, Spain
Maria J. Avedillo	Instituto de Microelectrónica de Sevilla (IMSE-CNM), Avda. Reina Mercedes s/n, 41012 Sevilla, Spain
Raúl Jiménez	Dpto. Ing. Electrónica de Sistemas Informáticos y Automática, Carr. Palos-La Rábida, 21071 Huelva, Spain
Esther Rodríguez-Villegas	Instituto de Microelectrónica de Sevilla (IMSE-CNM), Avda. Reina Mercedes s/n, 41012 Sevilla, Spain

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SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	Kai-Yeung Siu , Vwani Roychowdhury , Thomas Kailath, Toward massively parallel design of multipliers, Journal of Parallel and Distributed Computing, v.24 n.1, p.86-93, Jan. 1995 [doi>10.1006/jpdc.1995.1008]
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