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Generation of minimal size code for scheduling graphs
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Munich, Germany
Pages: 668 - 673  
Year of Publication: 2001
ISBN:0-7695-0993-2
Authors
C. Passerone  Politecnico di Torino, Italy
Y. Watanabe  Cadence Design Systems
L. Lavagno  Università di Udine, Italy
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 4,   Citation Count: 1
Additional Information:

references   cited by   index terms   collaborative colleagues   peer to peer  

Tools and Actions: Review this Article  

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
 
2
S. Bhattacharyya, J. Buck, S. Ha, and E. A. Lee. Generating compact code from dataflow specifications of multirate signal processing algorithms. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, March 1995.
3
Jordi Cortadella , Alex Kondratyev , Luciano Lavagno , Marc Massot , Sandra Moral , Claudio Passerone , Yosinori Watanabe , Alberto Sangiovanni-Vincentelli, Task generation and compile-time scheduling for mixed data-control embedded software, Proceedings of the 37th conference on Design automation, p.489-494, June 05-09, 2000, Los Angeles, California, United States  [doi>10.1145/337292.337553]
 
4
M. R. Garey, , and D. S. Johnson. Computers and Intractability. W.H. Freeman, 1979.
 
5
Edward Ashford Lee , David G. Messerschmitt, Static scheduling of synchronous data flow programs for digital signal processing, IEEE Transactions on Computers, v.36 n.1, p.24-35, Jan. 1987
 
6
H. Lekatsas and W. Wolf. SAMC: a code compression algorithm for embedded processors. IEEE Transactions on CAD, December 1999.
 
7
S. Liao, S. Devadas, and K. Keutzer. Code density optimization for embedded dsp processors using data compression techniques. IEEE Transactions on CAD, July 1998.
8
Bill Lin, Software synthesis of process-based concurrent programs, Proceedings of the 35th annual conference on Design automation, p.502-505, June 15-19, 1998, San Francisco, California, United States  [doi>10.1145/277044.277182]

CITED BY
 
Wolfgang Müller , Wolfgang Rosenstiel , Jürgen Ruf, References, SystemC: methodologies and applications, Kluwer Academic Publishers, Norwell, MA, 2003

INDEX TERMS

Primary Classification:
  G. Mathematics of Computing
  G.2 DISCRETE MATHEMATICS
      G.2.2 Graph Theory
          Subjects: Graph algorithms

Additional Classification:
  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Sequencing and scheduling

  G. Mathematics of Computing
  G.2 DISCRETE MATHEMATICS
      G.2.2 Graph Theory
          Subjects: Path and circuit problems


General Terms:
Algorithms, Performance, Theory

Collaborative Colleagues:
C. Passerone: colleagues
Y. Watanabe: colleagues
L. Lavagno: colleagues

Peer to Peer - Readers of this Article have also read:

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