Generalized reasoning scheme for redundancy addition and removal logic optimization

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Generalized reasoning scheme for redundancy addition and removal logic optimization

Full text

Pdf (94 KB)

Source

Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Pages: 391 - 397

Year of Publication: 2001

ISBN:0-7695-0993-2

Authors

J. Espejo	Universidad Carlos III de Madrid
L. Entrena	Universidad Carlos III de Madrid
E. San Millán	Universidad Carlos III de Madrid
E. Olias	Universidad Carlos III de Madrid

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 12, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Luis Entrena , Kwang-Ting Cheng, Sequential logic optimization by redundancy addition and removal, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.310-315, November 07-11, 1993, Santa Clara, California, United States
	2	S.-C. Chang, K.-T. Cheng, N.-S. Woo, M. Marek- Sadowska. "Post-layout logic restructuring using alternative wires". IEEE Transactions on CAD, vol.16, n. 6,
	3	S. C. Chang, M. Marek-Sadowska, K.-T. Cheng. "Perturb and Simplify: Multilevel Boolean Network Optimizer". IEEE Transactions on CAD, vol. 15, n. 12
	4	Wolfgang Kunz , Prem R. Menon, Multi-level logic optimization by implication analysis, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.6-13, November 06-10, 1994, San Jose, California, United States
	5	Wolfgang Kunz , Dominik Stoffel , Vishwani D. Agrawal , Randal E. Bryant, Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques, Kluwer Academic Publishers, Norwell, MA, 1997
	6	Shih-Chieh Chang , Lukas P. P. P. van Ginneken , Malgorzata Marek-Sadowska, Fast Boolean optimization by rewiring, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.262-269, November 10-14, 1996, San Jose, California, United States
	7	"SIS: A System for Sequential Circuit Synthesis" Report M92/41, University of California, Berkeley, May. 1992.
	8	L. Entrena , E. Olías , J. Uceda , J. Espejo, Timing optimization by an improved redundancy addition and removal technique, Proceedings of the conference on European design automation, p.342-347, September 1996, Geneva, Switzerland
	9	J. A. Espejo , L. Entrena , E. San Millán , E. Oliás, Functional extension of structural logic optimization techniques, Proceedings of the 2001 conference on Asia South Pacific design automation, p.467-472, January 2001, Yokohama, Japan [doi>10.1145/370155.370514]

CITED BY 2

	Enrique San Millán , Luis Entrena , José Alberto Espejo , Celia López, Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques, Journal of Systems Architecture: the EUROMICRO Journal, v.49 n.12-15, p.529-541, December 2003
	Enrique San Millán , Luis Entrena , José Alberto Espejo, On the optimization power of redundancy addition and removal techniques for sequential circuits, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California