High-level simulation of substrate noise generation from large digital circuits with multiple supplies

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High-level simulation of substrate noise generation from large digital circuits with multiple supplies

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Pages: 326 - 330

Year of Publication: 2001

ISBN:0-7695-0993-2

Authors

M. Badaroglu	IMEC v.z.w., Kapeldreef 75, B-3001 Leuven, Belgium and K.U., Leuven, Belgium
M. van Heijningen	IMEC v.z.w., Kapeldreef 75, B-3001 Leuven, Belgium
V. Gravot	IMEC v.z.w., Kapeldreef 75, B-3001 Leuven, Belgium
S. Donnay	IMEC v.z.w., Kapeldreef 75, B-3001 Leuven, Belgium
H. De Man	IMEC v.z.w., Kapeldreef 75, B-3001 Leuven, Belgium
G. Gielen	K.U., Leuven, Belgium
M. Engels	IMEC v.z.w., Kapeldreef 75, B-3001 Leuven, Belgium
I. Bolsens	IMEC v.z.w., Kapeldreef 75, B-3001 Leuven, Belgium

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 7, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	N. K. Verghese and D. J. Allstot, "Computer-aided design considerations for mixed-signal coupling in RF integrated circuits", in IEEE Journal of Solid-State Circuits, Vol. 33, No 3, pp. 314-323, March 1998.
	2	J. P. Costa, M. Chou and L. M. Silveira, "Efficient techniques for accurate modeling and simulation of substrate coupling in mixedsignal IC's", in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Sys., Vol. 18, No. 5, pp. 597-607, May 1999.
	3	M. K. Mayes and S. W. Chin, "All verilog mixed-signal simulator with analog behavioral and noise models", in Tech. Digest of the Symposium on VLSI Circuits, pp. 186-187, 1996.
	4	M. Nagata and A. Iawata, "Substrate noise simulation techniques for analog-digital mixed LSI design", IEICE Trans. Fundamentals, Vol. E82-A, pp. 271-278, February 1999.
	5	P. Miliozzi, L. Carboni, E. Charbon, and A. Sangiovanni- Vincentelli, "SUBWAVE: a methodology for modeling digital substrate noise injection in mixed-signal ICs", in Proc. 1996 IEEE Custom Integrated Circuits Conf., pp. 385-388, 1996.
	6	Marc van Heijningen , Mustafa Badaroglu , Stéphane Donnay , Marc Engels , Ivo Bolsens, High-level simulation of substrate noise generation including power supply noise coupling, Proceedings of the 37th conference on Design automation, p.446-451, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337539]
	7	D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, "Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits", IEEE Journal of Solid-State Circuits, Vol. 28, no. 4, pp. 420-430, April 1993.
	8	M. v. Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, and I. Bolsens, "Analysis and experimental verification of digital substrate noise generation for epi-type substrates", in IEEE Journal of Solid-State Circuits, vol. 35, pp. 1002-1008, July 2000.
	9	SubstrateStorm of Simplex, http://www.simplex.com/solutions/products/substratestorm.html

CITED BY 3

	Rajeev Murgai , Subodh M. Reddy , Takashi Miyoshi , Takeshi Horie , Mehdi Baradaran Tahoori, Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis, Proceedings of the conference on Design, automation and test in Europe, p.10610, February 16-20, 2004
	Yulei Weng , Alex Doboli, Digital cell macro-model with regular substrate template and EKV based MOSFET model, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	C. Soens , G. Van der Plas , P. Wambacq , S. Donnay, Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance, Proceedings of the conference on Design, Automation and Test in Europe, p.270-275, March 07-11, 2005