Low complexity FIR filters using factorization of perturbed coefficients

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Low complexity FIR filters using factorization of perturbed coefficients

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Pages: 268 - 272

Year of Publication: 2001

ISBN:0-7695-0993-2

Authors

C. Neau	ECE, Purdue University, West Lafayette, IN
K. Muhammad	Texas Instruments, Dallas, TX
K. Roy	ECE, Purdue University, West Lafayette, IN

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association

Publisher

IEEE Press Piscataway, NJ, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Sankarayya, N., Roy, K., and Bhattacharya, D. "Algorithms for Low-Power and High-Speed FIR Filter Realization Using Differential Coefficients". IEEE Trans. on Circuits and Systems, Vol. 44, No. 6, pp. 488-497, Jun. 1997.
	2	Khurram Muhammad , Kaushik Roy, Algorithmic and architectural techniques for low-power digital signal processing, 1999
	3	Mehendale, M., Sherlekar, S.D., and Venkatesh, G. "Coefficient Optimization for Low-Power Realization of FIR Filters", IEEE Workshop on VLSI Signal Processing, Japan, 1995.
	4	Ronald L. Graham , Donald E. Knuth , Oren Patashnik, Concrete Math, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1988
	5	Hartley, R. "Optimization of CSD Multipliers for Filter Design," IEEE Intl. Symposium on Circuits & Systems, Vol. 4, 1991. pp. 1992-1995.
	6	Azadet, K. and A.J. Nicole,"Low-Power Equilizer Architectures for High-Speed Modems," IEEE Communications Magazine, pp 118-126, Oct. 1998.
	7	Hawley, R., B. Wong, T. Lin, J. Laskowski, and H. Samueli. "Design Techniques for Silicon Compiler Implementations of High-Speed FIR Digital Filters," IEEE J. of Solid State Circuits, Vol 31, No. 5, May 1996, pp. 656-667.