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Clustering based fast clock scheduling for light clock-tree
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Munich, Germany
Pages: 240 - 245  
Year of Publication: 2001
ISBN:0-7695-0993-2
Authors
M. Saitoh  Tokyo Institute of Technology, Department of Communications and Integrated Systems, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8552, Japan
M. Azuma  Tokyo Institute of Technology, Department of Communications and Integrated Systems, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8552, Japan
A. Takahashi  Tokyo Institute of Technology, Department of Communications and Integrated Systems, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8552, Japan
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association
Publisher
IEEE Press  Piscataway, NJ, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 10,   Citation Count: 2
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
M. Azuma, M. Saito, and A. Takahashi. A clock-tree routing algorithm for low power using feasible range of clock schedule. SLDM 2000-SLDM-97 (2000-79), Information Processing Society of Japan, 2000. in Japanese.
 
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K. D. Boese and A. B. Kahng. Zero-skew clock routing trees with minimum wirelength. In Proc. IEEE 5th ASIC Conf., pages 1.1.1-1.1.5, 1992.
 
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R. B. Deokar and S. S. Sapatnekar. A graph-theoretic approach to clock skew optimization. In Proc. ISCAS '94, volume 1, pages 407-410, 1994.
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M. Edahiro and T. Yoshimura. Minimum path-length equidistant routing. In Proc. APCCAS 92, pages 41-46, 1992.
 
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K. Inoue, W. Takahashi, A. Takahashi, and Y. Kajitani. Schedule-clock-tree routing for semi-synchronous circuits. IEICE Transactions on Fundamentals, E82-A(11):2431- 2439, 1999.
 
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E. L. Lawler. Combinatorial Optimization, Networks and Matroids. Holt, Rinehart and Winston, New York, 1976.
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H. Mitsubayashi, A. Takahashi, and Y. Kajitani. Cost-radius balanced spanning/Steiner trees. IEICE Transactions on Fundamentals, E80-A(4):689-694, 1997.
 
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A. Takahashi and Y. Kajitani. Performance and reliability driven clock scheduling of sequential logic circuits. In Proc. ASP-DAC '97, pages 37-42, 1997.
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T. Yoda and A. Takahashi. Clock schedule design for minimum realization cost. IEICE Transactions on Fundamentals, E83-A(12):to appear, 2000.


Collaborative Colleagues:
M. Saitoh: colleagues
M. Azuma: colleagues
A. Takahashi: colleagues