PipeRench implementation of the instruction path coprocessor

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PipeRench implementation of the instruction path coprocessor

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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 147 - 158

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Yuan Chou	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Pazhani Pillai	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Herman Schmit	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
John Paul Shen	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 35, Citation Count: 5

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Linley Gwennap, "Intel's P6 Uses Decoupled Superscalar Design," in Microprocessor Report, Vol. 9, Issue 2, February 1995.
	2	Eric Rotenberg , Steve Bennett , James E. Smith, Trace cache: a low latency approach to high bandwidth instruction fetching, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.24-35, December 02-04, 1996, Paris, France
	3	Yuan Chou , John Paul Shen, Instruction path coprocessors, Proceedings of the 27th annual international symposium on Computer architecture, p.270-281, June 2000, Vancouver, British Columbia, Canada
	4	Seth Copen Goldstein , Herman Schmit , Matthew Moe , Mihai Budiu , Srihari Cadambi , R. Reed Taylor , Ronald Laufer, PipeRench: a co/processor for streaming multimedia acceleration, Proceedings of the 26th annual international symposium on Computer architecture, p.28-39, May 01-04, 1999, Atlanta, Georgia, United States
	5	H. Schmit, Incremental reconfiguration for pipelined applications, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.47, April 16-18, 1997
	6	Mihai Budiu , Seth Copen Goldstein, Fast compilation for pipelined reconfigurable fabrics, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.195-205, February 21-23, 1999, Monterey, California, United States [doi>10.1145/296399.296459]
	7	S. Patel, D. Friendly and Y. Patt, Critical Issues Regarding the Trace Cache Fetch Mechanism, Technical Report CSE- TR-335-97, University of Michigan, May 1997.
	8	Bryan Black , Bohuslav Rychlik , John Paul Shen, The block-based trace cache, Proceedings of the 26th annual international symposium on Computer architecture, p.196-207, May 01-04, 1999, Atlanta, Georgia, United States
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	26	P. Pillai, The Instruction Path Coprocessor Implemented on the PipeRench Fabric, CMuART Tech. Report, Carnegie Mellon Univ., 2000.

CITED BY 6

	Stephan Gatzka , Christian Hochberger, The AMIDAR Class of Reconfigurable Processors, The Journal of Supercomputing, v.32 n.2, p.163-181, May 2005
	Sami Yehia , Olivier Temam, From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation, ACM SIGARCH Computer Architecture News, v.32 n.2, p.238, March 2004
	Nathan Clark , Manjunath Kudlur , Hyunchul Park , Scott Mahlke , Krisztian Flautner, Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.30-40, December 04-08, 2004, Portland, Oregon
	Sebastian Lange , Udo Kebschull, Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems, Proceedings of the conference on Design, Automation and Test in Europe, p.10302, March 03-07, 2003
	Tameesh Suri , Aneesh Aggarwal, Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration, Proceedings of the 6th ACM conference on Computing frontiers, May 18-20, 2009, Ischia, Italy
	Domingo Benitez, Performance of reconfigurable architectures for image-processing applications, Journal of Systems Architecture: the EUROMICRO Journal, v.49 n.4-6, p.193-210, September 2003

INDEX TERMS

Primary Classification:
C. Computer Systems Organization
C.0 GENERAL
Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

Additional Classification:
B. Hardware
B.1 CONTROL STRUCTURES AND MICROPROGRAMMING
B.1.4 Microprogram Design Aids
Subjects: Optimization
B.8 Performance and Reliability

C. Computer Systems Organization

General Terms:
Design, Experimentation, Measurement, Performance, Theory

Collaborative Colleagues:

Yuan Chou: colleagues

Pazhani Pillai: colleagues

Herman Schmit: colleagues

John Paul Shen: colleagues

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