Allocation of FIFO structures in RTL data paths

ABSTRACT

Along with functional units, storage and interconnects contribute significantly to data path costs. This paper addresses the issue of reducing the costs of storage and interconnect. In a post-datapath synthesis phase, one or more queues can be allocated and variables bound to it, with the goal of reducing storage and interconnect costs. Further, in contrast to earlier work, we support “irregular” cdfgs and multicycle functional units for queue synthesis. Initial results on HLS benchmark examples have been encouraging, and show the potential of using queue synthesis to reduce datapath cost. A novel feature of our work is the formulation of the problem for a variety of FIFO structures with their own “queueing” criteria.

REFERENCES

• 1: AHMED, I. AND CHEN, C. Y. R. 1991. Post-processor for data path synthesis using multiport memories. In Proceedings of the Conference on ICCAD (ICCAD '91, Santa Clara, CA, Nov. 11-14), 276-279.
• 2: C. Y. Roger Chen , Mohammed Aloqeely, A new technique for exploiting regularity in data path synthesis, Proceedings of the conference on European design automation, p.394-399, September 19-23, 1994, Grenoble, France
• 3: Mohammed Aloqeely , C. Y. Roger Chen, Sequencer-based data path synthesis of regular iterative algorithms, Proceedings of the 31st annual conference on Design automation, p.155-160, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196317]
• 4: BALAKRISHNAN, M., BANERJI, D. K., MAJUMDAR, A. K., LINDERS, J. G., AND MAJITHIA, J. C. 1990. Allocation of multiport memories in data path synthesis. IEEE Trans. Comput.- Aided Des. 7, 4 (Apr. 1990), 536-540.
• 5: Daniel D. Gajski , Nikil D. Dutt , Allen C.-H. Wu , Steve Y.-L. Lin, High-level synthesis: introduction to chip and system design, Kluwer Academic Publishers, Norwell, MA, 1992
• 6: KHANNA, H. AND BALAKRISHNAN, M. 1996. Allocation of FIFO structures in RTL data paths. Tech. Rep. 96/2. Indian Institute of Technology, Delhi, India.
• 7: A. Kumar , V. Kashyap , S. D. Sherlekar , G. Venkatesh , S. Biwas , P. C. P. Bhatt , S. Kumar, Ideas: A Tool for VLSI CAD, IEEE Design & Test, v.6 n.5, p.50-57, September 1989 [doi>10.1109/54.43079]
• 8: Peter Marwedel, The mimola design system: Tools for the design of digital processors, Proceedings of the 21st conference on Design automation, p.587-593, June 25-27, 1984, Albuquerque, New Mexico, United States
• 9: RAO, M. V., BALAKRISHNAN, M., AND KUMAR, A. 1993. DESSERT: Design space exploration of RT-level components. In Proceedings of the Third Great Lakes Symposium on VLSI Design (Kalamazoo, MI, Mar. 5-6, 1993), 21-24.
• 10: TSENG, C. AND SIEWIOREK, D 1986. Automated synthesis of data paths on digital systems. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 5, 3 (July), 379-395.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION

General Terms:
Algorithms, Design

Keywords:
FIFO, ILP, RTL, data path, synthesis