High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies

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High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2000 international symposium on Low power electronics and design table of contents

Rapallo, Italy

Pages: 155 - 160

Year of Publication: 2000

ISBN:1-58113-190-9

Authors

Mohamed W. Allam	VLSI Research Group, University of Waterloo, Waterloo, ON, Canada N2L 3G1
Mohab H. Anis	VLSI Research Group, University of Waterloo, Waterloo, ON, Canada N2L 3G1
Mohamed I. Elmasry	VLSI Research Group, University of Waterloo, Waterloo, ON, Canada N2L 3G1

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

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Downloads (6 Weeks): 4, Downloads (12 Months): 27, Citation Count: 17

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ABSTRACT

A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-off between performance and noise margins in conventional CD-Domino logic while dissipating low dynamic power with minimal area overhead. A dual-threshold (MTCMOS) implementation of HS-Domino and DDCVS logic is also devised. This implementation achieves low leakage values during standby, while maintaining high performance and low dynamic power during the active mode.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H.Iwai, \CMOS Technology{Year 2010 and Beyond", IEEE JSSC, pp. 357{366, 1999.
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