Optimization of high-performance superscalar architectures for energy efficiency

ABSTRACT

In recent years reducing power has become a critical design goal for high-performance microprocessors. This work attempts to bring the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power-optimization at the micro-architectural level. First, major targets for power reduction are identified within superscalar microarchitecture, then an optimization of a superscalar micro-architecture is performed that generates a set of energy-efficient configurations forming a convex hull in the power-performance space. The energy-efficient families are then compared to find configurations that dissipate the lowest power given a performance target, or, conversely, deliver the highest performance given a power budget. Application of the developed methodology to a superscalar micro-architecture shows that at the architectural level there is a potential for reducing power up to 50%, given a performance requirement, and for up to 15% performance improvement, given a power budget.

REFERENCES

• 1: D. Burger and T. Austin. The SimpleScalar tool set, version 2.0. Technical Report 1342, University of Wisconsin- Madison, Computer Science Department, 1997.
• 2: Robert P. Colwell , Robert P. Nix , John J. O'Donnell , David B. Papworth , Paul K. Rodman, A VLIW architecture for a trace Scheduling Compiler, IEEE Transactions on Computers, v.37 n.8, p.967-979, August 1988 [doi>10.1109/12.2247]
• 3: K. Farkas. Memory-System Design Considerations for Dynamically-Scheduled Microprocessors. PhD thesis, University of Toronto, 1997.
• 4: James Farrell and Timothy Fischer. Issue logic for a 600- MHz out-of-order execution microprocessor. IEEE Journal of Solid-State Circuits, 33(5), May 1998.
• 5: Manoj Franklin, The multiscalar architecture, University of Wisconsin at Madison, Madison, WI, 1993
• 6: R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 31(9):1277-1283, September 1996.
• 7: R. E. Kessler, The Alpha 21264 Microprocessor, IEEE Micro, v.19 n.2, p.24-36, March 1999 [doi>10.1109/40.755465]
• 8: Ashok Kumar, The HP PA-8000 RISC CPU, IEEE Micro, v.17 n.2, p.27-32, March 1997 [doi>10.1109/40.592310]
• 9: J. Nelder and R. Mead. A simplex method for function minimization. Computer Journal, 7(4):308-313, 1965.
• 10: Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
• 11: J. Smith and G. Sohi. The microarchiteture of superscalar processors. Proceedings of the IEEE, December 1995.
• 12: M. Tremblay, D. Greenley, and K. Normoyle. The design of the microarchitecture of UltraSPARC-I TM. Proceedings of the IEEE, pages 16531-1663, December 1995.
• 13: Sriram Vajapeyam , Tulika Mitra, Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences, Proceedings of the 24th annual international symposium on Computer architecture, p.1-12, June 01-04, 1997, Denver, Colorado, United States
• 14: N. Vasseghi, K. Yeager, et al. 200-MHz superscalar RISC microprocessor. IEEE Journal of Solid-State Circuits, 31 (11): 1675-1685, November 1996.
• 15: Victor V. Zyuban , Peter M. Kogge, Inherently lower-power high-performance superscalar architectures, 2000
• 16: V. Zyuban , P. Kogge, The energy complexity of register files, Proceedings of the 1998 international symposium on Low power electronics and design, p.305-310, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280943]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Optimization

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Design, Measurement, Performance