Design issues for dynamic voltage scaling

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Design issues for dynamic voltage scaling

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2000 international symposium on Low power electronics and design table of contents

Rapallo, Italy

Pages: 9 - 14

Year of Publication: 2000

ISBN:1-58113-190-9

Authors

Thomas D. Burd	Berkeley Wireless Research Center, University of California, Berkeley 2108 Allston Way, Berkeley, CA
Robert W. Brodersen	Berkeley Wireless Research Center, University of California, Berkeley 2108 Allston Way, Berkeley, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 15, Downloads (12 Months): 149, Citation Count: 52

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ABSTRACT

Processors in portable electronic devices generally have a computational load which has time-varying performance requirements. Dynamic Voltage Scaling is a method to vary the processors supply voltage so that it consumes the minimal amount of energy by operating at the minimum performance level required by the active software processes. A dynamically varying supply voltage has implications on the processor circuit design and design flow, but with some minimal constraints it is straightforward to design a processor with this capability.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	T. Burd, T. Pering, A. Stratakos, R. Brodersen, "A Dynamic Voltage-Scaled Microprocessor System , 2000 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2000.
	2	Trevor Pering , Thomas Burd , Robert Brodersen, Voltage scheduling in the IpARM microprocessor system, Proceedings of the 2000 international symposium on Low power electronics and design, p.96-101, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344530]
	3	A. Stratakos, High-Efficiency, Low-Voltage DC-DC Conversion for Portable Applications, Ph.D. Thesis, University of California, Berkeley, Document No. UCB/ERL M98/32, 1998.
	4	Neil H. E. Weste , Kamran Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985
	5	S. Kawashima, et. al., "A Charge-Transfer Amplifier and an Encoded-Bus Architecture for Low-Power SRAM s , IEEE Journal of Solid State Circuits, Vol. 33, No. 5, May 1998, pp. 793-9.

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