Multiple Si layer ICs: motivation, performance analysis, and design implications

ABSTRACT

Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the 130 nm technology node, performance improvement of advanced VLSI is likely to begin to saturate unless a paradigm shift from present IC architecture is introduced. This paper presents a comprehensive analytical treatment of ICs with multiple Si layers (3-D ICs). It is shown that significant improvement in performance (more than 145%) and reduction in wire-limited chip area can be achieved with 3-D ICs with vertical inter-layer interconnects (VILICs). This analysis is based on dividing a chip into separate blocks, each occupying a separate physical level. A scheme to optimize interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis. Furthermore, thermal analysis of ICs with two Si layers is presented. It is demonstrated that using a thermally responsible design and/or a high-performance heat sinking technology, die temperatures for ICs with two Si layers can be reduced well below present die temperatures. Finally, implications of 3-D architecture on several circuit designs are also discussed.

REFERENCES

• 1: The National Technology Roadmap for Semiconductors, Technology Needs, 1997.
• 2: C. R. Barrett, "Microprocessor evolution and technology impact," Symp. VLSI Technol., Digest, 1993, pp. 7-10.
• 3: C. Hu, "MOSFET scaling in the next decade and beyond," Semiconductor International, pp. 105-114, 1994.
• 4: B. Davari, R. H. Dennard, and G. G. Shahidi, "CMOS scaling for high performance and low power-The next ten years," Proc. of the IEEE, vol. 83, no. 4, pp. 595-606, 1995.
• 5: G. A. Sai-Halasz, "Performance trends in high-end processors," Proc. of the IEEE, vol. 83, no. 1, pp. 20-36, 1995.
• 6: M. T. Bohr, "Interconnect scaling-the real limiter to high performance ULSI," IEDM Tech. Dig., 1995, pp. 241-244.
• 7: J. D. Meindl, "Low power microelectronics: retrospect and prospect," Proc. of the IEEE, vol. 83, no. 4, pp. 619-635, 1995.
• 8: S-Y Oh and K-J Chang, "2001 needs for multi-level interconnect technology," Circuits and Devices, pp. 16-21, 1995.
• 9: M. T. Bohr and Y. A. E1-Mansy, "Technology for advanced high-performance microprocessors," IEEE Trans. Electron Devices, vo145, no. 3, pp. 620-625, 1998.
• 10: D. Edelstein et al., "Full copper wiring in a sub-0.25 gm CMOS ULSI technology," IEDM Tech. Dig., 1997, pp. 773-776.
• 11: S. Venkatesan et al., "A high performance 1.8V, 0.20 gm CMOS technology with copper metallization," IEDM Tech. Dig., 1997, pp. 769-772.
• 12: E. M. Zielinski et al., "Damascene integration of copper and ultra-low-k xerogel for high performance interconnects," IEDM Tech. Dig., 1997, pp. 936-938.
• 13: N. Rohrer et al., "A 480MHz RISC microprocessor in a 0.12 gm Leff CMOS technology with copper interconnects," Int. Solid-State Circuits Conf., Tech. Digest, 1998, pp. 240-241.
• 14: B. Zhao et al., " A Cu/low-k dual damascene interconnect for high performance and low cost integrated circuits," Symp. VLSI Technology, Tech. Digest, 1998, pp. 28-29.
• 15: W. J. Dally, "Interconnect-limited VLSI architecture," Int. Interconnect Technology Conf. Proceedings, 1999, pp. 15-17.
• 16: M. W. Geis, D. C. Flanders, D. A. Antoniadis, and H. I. Smith, "Crystalline silicon on insulators by graphoepitaxy," IEDM Tech. Dig., 1979, pp. 210-212.
• 17: J. P. Colinge and E. Demoulin, "ST-CMOS (Stacked Transistor CMOS): a doublepoly-NMOS-compatible CMOS technology," IEDM Tech. Dig., 1981, pp. 557- 560.
• 18: G. T. Goeloe, E. W. Maby, D. J. Silversmith, R. W. Mountain, and D. A. Antoniadis, "Vertical single-gate CMOS inverters on laser-processed multilayer substrates," IEDM Tech. Dig., 1981, pp. 554-556.
• 19: S. Kawamura, N. Sasaki, T. Iwai, M. Nakano, and M. Takagi, "Three-dimensional CMOS IC's fabricated by using beam recrystallization," IEEE Electron Device Lett., vol. EDL-4, no. 10, pp. 366-368, 1983.
• 20: S. Akiyama, S. Ogawa, M. Yoneda, N. Yoshii, and Y. Terui, "Multilayer CMOS device fabricated on laser recrystallized silicon islands," IEDM Tech. Dig., 1983, pp. 352-355.
• 21: M. Nakano, "3-D SOI/CMOS," IEDM Tech. Dig., 1984, pp. 792-795.
• 22: K. Sugahara, T. Nishimura, S. Kusunoki, Y. Akasaka, and H. Nakata, "SOI/SOI/Bulk-Si triple level structure for three-dimensional devices," IEEE Electron Device Lett., vol. EDL-7, no. 3, pp. 193-195, 1986.
• 23: Y. Akasaka and T. Nishimura, "Concept and basic technologies for 3-D IC structure," IEDM Tech. Dig., 1986, pp. 488-491.
• 24: S. Tatsuno, "Japan's push into creative semiconductor research: 3-dimension IC's," Solid State Technology, March 30, pp. 29-30, 1987.
• 25: T. Nishimura, Y. Inoue, K. Sugahara, S. Kusunoki, T. Kumamoto, S. Nakagawa, M. Nakaya, Y. Horiba, and Y. Akasaka, "Three dimensional IC for high performance image signal processor," IEDM Tech. Dig., 1987, pp. 111-114.
• 26: T. Kunio, K. Oyama, Y. Hayashi, and M. Morimoto, "Three dimensional ICs, having four stacked active device layers," IEDM Tech. Dig., 1989, pp. 837-840.
• 27: Stephen Strickland , Erhan Ergin , David R. Kaeli , Paul Zavracky, VLSI design in the 3rd dimension, Integration, the VLSI Journal, v.25 n.1, p.1-16, Sept. 1998 [doi>10.1016/S0167-9260(98)00006-6]
• 28: D. Antoniadis, "3-dimensional 25 nm- scale CMOS technology," Advanced Microelectronics Program Review Proceedings Book, Sept. 1-2, Lexington, MA, 1998.
• 29: V. Subramanian and K. C. Saraswat, "High-performance germanium-seeded laterally crystallized TFT's for vertical device integration," IEEE Trans. Electron Devices, vol. 45, no. 9, pp. 1934-1939, 1998.
• 30: G. W. Neudeck, S. Pae, J. P. Denton, and T. Su, "Multiple layers of silicon-oninsulator for nanostructure devices," J. Vac. Sci. Technol. B 17(3), pp. 994-998, 1999.
• 31: K. C. Saraswat, S. J. Souri, V. Subramanian, A. R. Joshi, and A. W. Wang, "Novel 3-D Structures," IEEE Int. SO1 Conf., 1999, pp. 54-55.
• 32: S. A. Kuhn, M. B. Kleiner, P. Ramm, and W. Weber, "Performance modeling of the interconnect structure of a three-dimensional integrated RISC processor/cache system," IEEE Trans. Components, Packaging, and Manufacturing Technology- PartB, vol. 19, no. 4, pp. 719-727, 1996.
• 33: M. B. Kleiner, S. A. Kuhn, P. Ramm, and W. Weber, "Performance improvement of the memory hierarchy of RISC-systems by application of 3-D technology," IEEE Trans. Components, Packaging, and Manufacturing Technology-Part B, vol. 19, no. 4, pp. 709-718, 1996.
• 34: S. J. Souri and K. C. Saraswat, "Interconnect performance modeling for 3D integrated circuits with multiple Si layers," Int. Interconnect Technology Conf. Proceedings, 1999, pp. 24-26.
• 35: A. Rahman, A. Fan, J. Chung, and R. Reif, "Wire-length distribution of threedimensional integrated circuits," Int. Interconnect Technology Conf. Proceedings, 1999, pp. 233-235.
• 36: R. Zhang, K. Roy, and D. B. Jones, "Architecture and performance of 3- dimensional SOI circuits," IEEE Int. SO1 Conf., 1999, pp. 44-45.
• 37: A. Kohno, T. Sameshima, N. Sano, M. Sekiya, and M. Hara, "High performance poly-Si TFTs fabricated using pulsed laser annealing and remote plasma CVD with low temperature processing," IEEE Trans. Electron Devices, vo142, no. 2, pp. 251- 257, 1995.
• 38: M. A. Crowder, P. G. Carey, P. M. Smith, R. S. Sposili, H. S. Cho, and J. S. Ira, "Low-temperature single crystal Si TFT's fabricated on Si-films processed via sequential lateral solidification," IEEE Electron Device Lett., vol. 19, no. 8, pp. 306-308, 1986.
• 39: H-Y. Lin, C-Y. Chang, T. F. Lei, J-Y. Cheng, H-C. Tseng, and L-P. Chen, "Characterization of polycrystalline silicon thin film transistors fabricated by ultrahigh-vacuum chemical vapor deposition and chemical mechanical polishing," Jpn. J. Appl. Phys., Part 1, vol.36, (no.7A), pp. 4278-4282, July 1997.
• 40: T. Noguchi, "Appearance of single-crystalline properties in fine-patterened Si thin film transistors (TFTs) by solid phase crystallization (SPC)," Jpn. J. Appl. Phys., Part 2, no.llA, vol.32, pp. 1584-1587, Nov. 1993.
• 41: T. W. Little, H. Koike, K. Takahara, T. Nakazawa, and H. Oshima, "A 9.5-in. 1.3- Mpixel low-temperature poly-Si TFT-LCD fabricated by solid-phase crystallization of very thin films and an ECR-CVD gate insulator," J. Society for Information Display, 1/2, pp. 203-209, 1993.
• 42: N. Yamauchi, "Polycrystalline silicon thin films processed with silicon ion implantation and subsequent solid-phase crystallization: theory, experiments, and thin-film transistor applications," J. Appl. Phys., 75(7), pp. 3235-3257, 1994.
• 43: Dimitrios N. Kouvatsos , Apostolos T. Voutsas , Miltiadis K. Hatalis, Polycrystalline silicon thin film transistors fabricated in various solid phase crystallized films deposited on glass substrates, Journal of Electronic Materials, v.28 n.1, p.19-25, Jan. 1999 [doi>10.1007/s11664-999-0189-5]
• 44: J. A. Tsai, A. J. Tang, T. Noguchi, and R. Reif, "Effects of Ge on material and electrical properties of polycrystalline Sil.xGex for thin film transistors," J. Electrochem. Soc., vol. 142, no. 9, pp. 3220-3225, 1995.
• 45: S-W. Lee and S-K. Joo, "Low temperature poly-Si thin film transistor fabrication by metal-induced lateral crystallization," IEEE Electron Device Lett., vol. 17, no. 4, pp. 160-162, 1983.
• 46: S. Y. Yoon, S. K. Kim, J. Y. Oh, Y. J. Choi, W. S. Shon, C. O. Kim, and J. Jang, "A high-performance polycrystalline silicon thin-film transistor using metalinduced crystallization with Ni solution," Jpn. J. Appl. Phys., Part 1, pp. 7193- 7197, Dec. 1998.
• 47: A. R. Joshi and K. C. Saraswat, "Sub-micron thin film transistors with metal induced lateral crystallization," Abstract no. 1358, Proc. 196th Meeting of the Electrochemical Society, Honolulu, HI, 1999.
• 48: J. Nakata and K. Kajiyama, "Novel low-temperature recrystalization of amorphous silicon by high energy beam," Appl. Phys. Lett., pp. 686-688, 1982.
• 49: Y. W. Choi, J. N. Lee, T. W. Jang, and B. T. Ahn, "Thin-film transistors fabricated with poly-Si films crystallized at low temperature by microwave annealing," IEEE Electron Device Lett., vol. 20, no. 1, pp. 2-4, 1999.
• 50: A. Heya, A. Masuda, and H. Matsumura, "Low-temperature crystallization of amorphous silicon using atomic hydrogen generated by catalytic reaction on heated tungsten," Appl. Phys. Lett., vol. 74, no. 15, pp. 2143-2145, 1999.
• 51: R K. Watts and J. T. C. Lee, "Tenth-micron polysilicon thin-film transistors," IEEE Electron Device Lett., vol. 14, no. 11, pp. 515-517, 1993.
• 52: M. Rodder and S. Aur, "Utilization of plasma hydrogenation in stacked SRAMs with poly-Si PMOSFETs and bulk Si NMOSFETs," IEEE Electron Device Lett., vol. 12, no. 5, pp. 233-235, 1991.
• 53: T. Yamanaka et al., "Advanced TFT SRAM cell technology using a phase-shift lithography," IEEE Trans. Electron Devices, vol. 42, no. 7, pp. 1305-1312, 1995.
• 54: M. Cao, T. Zhao, K. C. Saraswat, and J. D. Plummer, "A simple EEPROM cell using twin polysilicon thin film transistor," IEEE Electron Device Lett., vol. 15, no. 8, pp. 304-306, 1994.
• 55: P. Ramm , D. Bollmann , R. Braun , R. Buchner , U. Cao-Minh , M. Engelhardt , G. Errmann , T. Graßl , H. Hü , G. Kawala , M. Kleiner , A. Klumpp , S. Kühn , C. Landesberger , H. Lezec , W. Muth , W. Pamler , R. Popp , E. Renner , G. Ruhl , K. Hieberßbner, Three dimensional metallization for vertically integrated circuits, Microelectronic Engineering, 37-38, p.39-47, 1997 [doi>10.1016/S0167-9317(97)00092-0]
• 56: J. A. Davis, V. K. De, and J. D. Meindl, "A stochastic wire-length distribution for gigascale integration (GSI) - Part II: Applications to clock frequency, power dissipation, and chip size estimation," IEEE Trans. Electron Devices, Vol. 45, no. 3, March 1998.
• 57: L. Robinson, L. A. Glasser, and D. A. Antoniadis, "A simple interconnect delay model for multilayer integrated circuits," IEEE VMIC Conf., 1986.
• 58: B. S. Landman, and R. L. Russo, "On a pin versus block relationship for partitions of logic graphs," IEEE Trans. Computers, vol. C-20, no. 12, Dec. 1971.
• 59: J. A. Davis, V. K. De, and J. D. Meindl, "A stochastic wire-length distribution for gigascale integration (GSI) - Part I: Derivation and validation," IEEE Trans. Electron Devices, Vol. 45, no. 3, March 1998.
• 60: S. A. Kuhn, M. B. Kleiner, P. Ramm, and W. Weber, "Thermal analysis of vertically integrated circuits," IEDM Tech. Dig., 1995, pp. 487-490.
• 61: K. Banerjee, "Thermal effects in deep submicron VLSI interconnects," Tutorial Notes, IEEE International Symposium on Quality Electronic Design, March 20-22, 2000.
• 62: K. E. Goodson and Y. S. Ju, "Heat conduction in novel electronic films," Annu. Rev. Mater. Sci., 29: pp. 261-293, 1999.
• 63: K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu, "The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal," IEDM Tech. Dig., 1996, pp. 65-68.
• 64: Kaustav Banerjee , Amit Mehrotra , Alberto Sangiovanni-Vincentelli , Chenming Hu, On thermal effects in deep sub-micron VLSI interconnects, Proceedings of the 36th ACM/IEEE conference on Design automation, p.885-891, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310093]
• 65: D. B. Tuckerman, R. F. W. Pease, "High-performance heat sinking for VLSI," IEEE Electron Device Lett., vol. EDL-2, no.5, pp. 126-129, 1981.
• 66: S. A. Kuhn, M. B. Kleiner, P. Ramm, and W. Weber, "Interconnect capacitances, crosstalk, and signal delay in vertically integrated circuits," IEDM Tech. Dig., 1995, pp. 487-490.
• 67: Ralph H. J. M. Otten , Robert K. Brayton, Planning for performance, Proceedings of the 35th annual conference on Design automation, p.122-127, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277071]
• 68: Jason Cong , Lei He, An efficient technique for device and interconnect optimization in deep submicron designs, Proceedings of the 1998 international symposium on Physical design, p.45-51, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274542]
• 69: P. D. Fisher, "Clock cycle estimation for future microprocessor generations," Technical Report, SEMATECH 1997.
• 70: D. Greenhill et al, "A 330 MHz 4-way superscalar microprocessor," ISSCC, Digest of Tech. Papers, 1997, pp. 166-167.
• 71: B. Razavi, "Challenges and Trends in RF Design," Proc. 9'h Annual IEEE Int. ASIC Conf. and Exhibit, 1996, pp. 81-86.

INDEX TERMS

Primary Classification:
  J. Computer Applications

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)
  B.8 Performance and Reliability

  C. Computer Systems Organization