Planning buffer locations by network flows

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Planning buffer locations by network flows

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International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents

San Diego, California, United States

Pages: 180 - 185

Year of Publication: 2000

ISBN:1-58113-191-7

Authors

Xiaoping Tang	Department of Computer Sciences, University of Texas at Austin, Austin, TX
D. F. Wong	Department of Computer Sciences, University of Texas at Austin, Austin, TX

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 15, Citation Count: 21

Additional Information:

references cited by collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Jason Cong , Tianming Kong , David Zhigang Pan, Buffer block planning for interconnect-driven floorplanning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.358-363, November 07-11, 1999, San Jose, California, United States
	2	Semiconductor Industry Association, National Technology Roadmap for Semiconductors, 1997.
	3	Jason Cong , Zhigang Pan , Lei He , Cheng-Kok Koh , Kei-Yong Khoo, Interconnect design for deep submicron ICs, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.478-485, November 09-13, 1997, San Jose, California, United States
	4	J. Cong, "Challenges and opportunities for design innovations in nanometer technologies", SRC Working Papers, http : //www:src:org/prgmgmt/frontier:dgw, Dec. 1997.
	5	L.P.P.P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay", ISCAS-90, pp. 865-868, 1990.
	6	John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin, Optimal wire sizing and buffer insertion for low power and a generalized delay model, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.138-143, November 05-09, 1995, San Jose, California, United States
	7	Takumi Okamoto , Jason Cong, Buffered Steiner tree construction with wire sizing for interconnect layout optimization, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.44-49, November 10-14, 1996, San Jose, California, United States
	8	Chris C. N. Chu , D. F. Wong, Closed form solution to simultaneous buffer insertion/sizing and wire sizing, Proceedings of the 1997 international symposium on Physical design, p.192-197, April 14-16, 1997, Napa Valley, California, United States [doi>10.1145/267665.267712]
	9	C. Chu and D.F. Wong, "A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing," IEEE Transactions on Computer-Aided Design, Vol. 18, No. 6, 1999.
	10	Charles Alpert , Anirudh Devgan, Wire segmenting for improved buffer insertion, Proceedings of the 34th annual conference on Design automation, p.588-593, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266291]
	11	Hai Zhou , D. F. Wong , I-Min Liu , Adnan Aziz, Simultaneous routing and buffer insertion with restrictions on buffer locations, Proceedings of the 36th ACM/IEEE conference on Design automation, p.96-99, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309885]
	12	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	13	R.K. Ahuja, T.L. Magnanti, and J.B. Orlin, Network Flows, Prentice Hall, 1993.
	14	Mark de Berg , Marc van Kreveld , Mark Overmars , Otfried Schwarzkopf, Computational geometry: algorithms and applications, Springer-Verlag New York, Inc., Secaucus, NJ, 1997
	15	Probir Sarkar , Vivek Sundararaman , Cheng-Kok Koh, Routability-driven repeater block planning for interconnect-centric floorplanning, Proceedings of the 2000 international symposium on Physical design, p.186-191, May 2000, San Diego, California, United States [doi>10.1145/332357.332398]

CITED BY 21

	Yuchun Ma , Xianlong Hong , Sheqin Dong , Song Chen , Yici Cai , Chung-Kuan Cheng , Jun Gu, Buffer allocation algorithm with consideration of routing congestion, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.621-623, January 27-30, 2004, Yokohama, Japan
	Yuchun Ma , Xianlong Hong , Sheqin Dong , Song Chen , Yici Cai , C. K. Cheng , Jun Gu, Dynamic global buffer planning optimization based on detail block locating and congestion analysis, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Ou He , Sheqin Dong , Jinian Bian , Yuchun Ma , Xianlong Hong, An effective buffer planning algorithm for IP based fixed-outline SOC placement, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Ali Jahanian , Morteza Saheb Zamani, Improved timing closure by early buffer planning in floor-placement design flow, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Charles J. Alpert , Jiang Hu , Sachin S. Sapatnekar , Paul Villarrubia, A practical methodology for early buffer and wire resource allocation, Proceedings of the 38th conference on Design automation, p.189-194, June 2001, Las Vegas, Nevada, United States
	Shu-Min Li , Yih-Huai Cherng , Yao-Wen Chang, Noise-aware buffer planning for interconnect-driven floorplanning, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Bo Hu , Malgorzata Marek-Sadowska, FAR: fixed-points addition & relaxation based placement, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Song Chen , Xianlong Hong , Sheqin Dong , Yuchun Mal , Yici Cai , Chung-Kuan Cheng , Jun Gu, A buffer planning algorithm based on dead space redistribution, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Song Chen , Xianlong Hong , Sheqin Dong , Yuchun Ma , Yici Cai , Chung-Kuan Cheng , Jun Gu, A buffer planning algorithm with congestion optimization, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.615-620, January 27-30, 2004, Yokohama, Japan
	Yuchun Ma , Xianlong Hong , Sheqin Dong , Song Chen , Yici Cai , C. K. Cheng , Jun Gu, An integrated floorplanning with an efficient buffer planning algorithm, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Chiu Wing Sham , Evangeline F. Y. Young, Routability driven floorplanner with buffer block planning, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Iris Hui-Ru Jiang , Yao-Wen Chang , Jing-Yang Jou , Kai-Yuan Chao, Simultaneous floorplanning and buffer block planning, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Hua Xiang , Xiaoping Tang , Martin D. F. Wong, An algorithm for integrated pin assignment and buffer planning, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.3, p.561-572, July 2005
	Hua Xiang , D. F. Wong , Xiaoping Tang, An algorithm for integrated pin assignment and buffer planning, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	I-Min Liu , Hung-Ming Chen , Tan-Li Chou , Adnan Aziz , D. F. Wong, Integrated power supply planning and floorplanning, Proceedings of the 2001 conference on Asia South Pacific design automation, p.589-594, January 2001, Yokohama, Japan
	Yi-Hui Cheng , Yao-Wen Chang, Integrating buffer planning with floorplanning for simultaneous multi-objective optimization, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.624-627, January 27-30, 2004, Yokohama, Japan
	Keith W. C. Wong , Evangeline F. Y. Young, Fast buffer planning and congestion optimization in interconnect-driven floorplanning, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Feodor F. Dragan , Andrew B. Kahng , Ion Mandoiu , Sudhakar Muddu , Alexander Zelikovsky, Provably good global buffering by multi-terminal multicommodity flow approximation, Proceedings of the 2001 conference on Asia South Pacific design automation, p.120-125, January 2001, Yokohama, Japan
	Christoph Albrecht , Andrew B. Kahng , Ion Mandoiu , Alexander Zelikovsky, Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.580, January 07-11, 2002
	Jason Cong , Tianming Kong , Zhigang (David) Pan, Buffer block planning for interconnect planning and prediction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.929-937, 12/1/2001
	Feodor F. Dragan , Andrew B. Kahng , Ion Măndoiu , Sudhakar Muddu , Alexander Zelikovsky, Provably good global buffering using an available buffer block plan, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California

Collaborative Colleagues:

Xiaoping Tang: colleagues

D. F. Wong: colleagues

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