Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	L. Chang et al., "A new modeling methodology for copper on-chip interconnects", to appear in the proceedings of 2000 International Symposium on Quality of Electronic Design (ISQED 2000).
	2	A. E. Ruehli, "Equivalent Circuit Models for Three Dimensional Multiconductor Systems", IEEE Transactions on Microwave Theory and Technology, MTT-22 (3), pp. 216-221, March 1974.
	3	L. Chang et al., "Frequency Dependence of Resistance and Inductance Effects in On-Chip Interconnects", to appear in the Proceedings of DesignCon Conference, Santa Clara, California, January 2000.
	4	Yehia Massoud , Steve Majors , Tareq Bustami , Jacob White, Layout techniques for minimizing on-chip interconnect self inductance, Proceedings of the 35th annual conference on Design automation, p.566-571, June 15-19, 1998, San Francisco, California, United States  [doi>10.1145/277044.277194]
	5	L. Chang et al., "Modeling and Managing On-Chip Interconnect Inductance", Proceedings of VLSI Multilevel Interconnection Conference, pp. 457-462, September 1999.
	6	Ansoft Corp., Maxwell SpiceLink Software, 1999.
	7	J. White et al., FastHenry Software, 1992.
	8	K. Chang et al., "System and Method for Extracting Parasitic Impedance from an Integrated Circuit Layout", United States Patent 5901063, May 4, 1999.

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