| Pseudo pin assignment with crosstalk noise control |
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International Symposium on Physical Design
archive
Proceedings of the 2000 international symposium on Physical design
table of contents
San Diego, California, United States
Pages: 41 - 47
Year of Publication: 2000
ISBN:1-58113-191-7
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Authors
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Chin-Chih Chang
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UCLA Computer Science Department, Los Angeles, CA
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Jason Cong
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UCLA Computer Science Department, Los Angeles, CA
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Downloads (6 Weeks): 3, Downloads (12 Months): 7, Citation Count: 6
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Kamal Chaudhary , Akira Onozawa , Ernest S. Kuh, A spacing algorithm for performance enhancement and cross-talk reduction, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.697-702, November 07-11, 1993, Santa Clara, California, United States
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H. H. Chen and C. K. Wong. Wiring and crosstalk avoidance in multi-chip module design. In Proceedings of the IEEE 1992 Custom Integrated Circuits Conference, pages 28.6.1-28.6.4, 1992.
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J. Cong. Pin assignment with global routing for general cell designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 10(11):1401-1412, November 1991.
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Jason Cong , Jie Fang , Kei-Yong Khoo, An implicit connection graph maze routing algorithm for ECO routing, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.163-167, November 07-11, 1999, San Jose, California, United States
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Jason Cong , Lei He , Andrew B. Kahng , David Noice , Nagesh Shirali , Steve H.-C. Yen, Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology, Proceedings of the 34th annual conference on Design automation, p.627-632, June 09-13, 1997, Anaheim, California, United States
[doi> 10.1145/266021.266303]
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T. Gao and C. L. Liu. Minimum crosstalk channel routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(5):465-474, May 1996.
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W.-C. Kao and T.-M. Parng. Cross point assignment with global rerouting for general-architecture designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14(3):337-348, March 1995.
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H. Kawaguchi and T. Sakurai. Delay and noise formulas for capacitively coupled distributed RC lines. In Proc. Asia South Pacific Design Automation Conf., pages 35-43, 1998.
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D. P. Lapotin. Early assessment of design, packaging and technology tradeoffs. International Journal of High Speed Electronics, 2(4):209-233, 1991.
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J. K. Ousterhout. Corner stitching: a data-structuring technique for VLSI layout tools. IEEE Transactions on Computer-Aided Design, CAD-3(1):87-99, 1984.
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T. Sakurai. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs. IEEE Trans. on Electron Devices, 40:118-124, 1993.
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Tilmann Stöhr , Markus Alt , Asmus Hetzel , Jürgen Koehl, Analysis, reduction and avoidance of crosstalk on VLSI chips, Proceedings of the 1998 international symposium on Physical design, p.211-218, April 06-08, 1998, Monterey, California, United States
[doi> 10.1145/274535.274566]
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Hsiao-Ping Tseng , Louis Scheffer , Carl Sechen, Timing and crosstalk driven area routing, Proceedings of the 35th annual conference on Design automation, p.378-381, June 15-19, 1998, San Francisco, California, United States
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A. Vittal and M. Marek-Sadowska. Crosstalk reduction for VLSI. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 16(3):290-298, March 1997.
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Tianxiong Xue , Ernest S. Kuh , Dongsheng Wang, Post global routing crosstalk risk estimation and reduction, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.302-309, November 10-14, 1996, San Jose, California, United States
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CITED BY 6
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Shabbir Batterywala , Narendra Shenoy , William Nicholls , Hai Zhou, Track assignment: a desirable intermediate step between global routing and detailed routing, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.59-66, November 10-14, 2002, San Jose, California
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