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Requirements for models of achievable routing
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Source International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents
San Diego, California, United States
Pages: 4 - 11  
Year of Publication: 2000
ISBN:1-58113-191-7
Authors
Andrew B. Kahng  UCLA CS Dept., 3731 Boelter Hall, LA, CA
Stefanus Mantik  UCLA CS Dept., 3731 Boelter Hall, LA, CA
Dirk Stroobandt  Ghent University, ELIS Dept., Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 4,   Citation Count: 13
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Publishing Co., 1990.
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Q. Chen, J. Davis, P. Zarkesh-Ha and J. Meindl, "Via Impact and Via-Limited Chip Size", Private communication, Georgia Institute of Technology, 1999.
 
5
P. Chong and R. K. Brayton, "Estimating and Optimizing Routing Utilization in DSM Design", Workshop notes Intl. Workshop on System-Level Interconnect Prediction, D. Stroobandt and A. B. Kahng, editors, 1999, pp. 97-102.
 
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J. A. Davis, V. K. De and J. D. Meindl, "A Stochastic Wirelength Distribution for Gigascale Integration (GSI) - Part I: Derivation and Validation", IEEE Trans. on Electron Devices, vol. 45(3), 1998, pp. 580-589.
 
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W. E. Donath, "Placement and Average Interconnection Lengths of Computer Logic", IEEE Trans. on Circuits ~4 Syst., vol. CAS-26, 1979, pp. 272-277.
 
9
W. E. Donath, "Wire Length Distribution for Placements of Computer Logic", IBM J. of Research and Development, vol. 25, 1981, pp. 152-155.
 
10
J. C. Eble, V. K. De, D. S. Wills and J. D. Meindl, "A Generic System Simulator (GENESYS) for ASIC Technology and Architecture Beyond 2001", Proc. 9th Annual IEEE Intl. ASIC Conf., 1996, pp. 193-196.
 
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J. Griffith, G. Robins, J. S. Salowe and T. Zhang, "Closing the Gap: Near-Optimal Steiner Trees in Polynomial Time", IEEE Trans. on Computer-Aided Design of Integrated Circults and Systems, vol. 13(11), 1994, pp. 1351-1365.
 
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B. S. Landman and R. L. Russo, "On a Pin Versus Block Relationship for Partitions of Logic Graphs", IEEE Trans. on Computer, vol. C-20, 1971, pp. 1469-1479.
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15
G.A. Sai-Halasz, "Performance Trends in High-Performance Processors", Proc. of IEEE, 1995, pp. 20-36.
 
16
D. Stroobandt and J. Van Campenhout, "Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle", VLSI Design, Special Issue on Physical Design in Deep Submicron, vol. 10, 1999.
17

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Andrew B. Kahng: colleagues
Stefanus Mantik: colleagues
Dirk Stroobandt: colleagues

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