| Field programmable port extender (FPX) for distributed routing and queuing |
| Full text |
Pdf
(710 KB)
|
| Source
|
International Symposium on Field Programmable Gate Arrays
archive
Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
table of contents
Monterey, California, United States
Pages: 137 - 144
Year of Publication: 2000
ISBN:1-58113-193-3
|
|
Authors
|
|
John W. Lockwood
|
Department of Computer Science, Applied Research Lab, Washington University, 1 Brookings Drive, Saint Louis, MO
|
|
Jon S. Turner
|
Department of Computer Science, Applied Research Lab, Washington University, 1 Brookings Drive, Saint Louis, MO
|
|
David E. Taylor
|
Department of Computer Science, Applied Research Lab, Washington University, 1 Brookings Drive, Saint Louis, MO
|
|
| Sponsor |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 8
|
|
|
ABSTRACT
Field Programmable Gate Arrays (FPGAs) are being used to provide fast Internet Protocol (IP) packet routing and advanced queuing in a highly scalable network switch. A new module, called the Field-programmable Port Extender (FPX), is being built to augment the Washington University Gigabit Switch (WUGS) with reprogrammable logic.FPX modules reside at the edge of the WUGS switching fabric. Physically, the module is inserted between an optical line card and the WUGS gigabit switch back-plane. The hardware used for this project allows ports of the switch populated with an FPX to operate at rates up to 2.4 Gigabits/second. The aggregate throughput of the system scales with the number of switch ports.Logic on the FPX module is implemented with two FPGA devices. The first device is used to interface between the switch and the line card, while the second is used to prototype new networking functions and protocols. The logic on the second FPGA can be reprogrammed dynamically via control cells sent over the network.The flexibility of the FPX has made the card of interest for several networking applications. This year, fifty FPX hardware modules will be fabricated and distributed to researchers at eight universities around the country who are interested in experimenting with reprogrammable networks and per-flow queuing mechanisms. The FPX hardware will first be used to implement fast IP lookup algorithms and distributed input queueing.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
J. W. Lockwood, "Illinois Pulsar-based Optical Interconnect (iPOINT)." http://ipoint.vlsi.- uiuc.edu, Sept. 1999.
|
| |
2
|
J. W. Lockwood, H. Duan, J. J. Morikuni, S. M. Kang, S. Akkineni, and 1t. H. Campbell, "Scalable optoelectronic ATM networks: The iPOINT fully functional testbed," IEEE Journal of Lightwave Technology, pp. 1093-1103, June 1995.
|
| |
3
|
H. Duan, J. W. Lockwood, and S. M. Kang, "FPGA prototype queueing module for high performance ATM switching," in Proceedings of the Seventh Annual IEEE International ASIC Conference, (Rochester, NY), pp. 429-432, Sept. 1994.
|
| |
4
|
M. J. Karol, M. G. Hluchyj, and S. P. Morgan, "Input vs. output queueing in space division packet switching," IEEE Tfunsactions on Communicationa, vol. Com-35, pp. 1347-1356, Dec. 1987.
|
| |
5
|
|
| |
6
|
|
| |
7
|
J. S. Turner, "Gigabit Technology Distribution Program." http:/www.arl.wustl.edu/- gigabitkits/kits.html, Aug. 1999.
|
| |
8
|
W. N. Eatherton, "Hardware-Based Internet Protocol Prefix Lookups." thesis, Washington University in St. Louis, 1998.
|
 |
9
|
Marcel Waldvogel , George Varghese , Jon Turner , Bernhard Plattner, Scalable high speed IP routing lookups, Proceedings of the ACM SIGCOMM '97 conference on Applications, technologies, architectures, and protocols for computer communication, p.25-36, September 14-18, 1997, Cannes, France
|
| |
10
|
N. McKeown, V. Anantharam, and J. Walrand, "Achieving 100% throughput in an input-queued switch," in INFOCOM'96, Mar. 1996.
|
| |
11
|
H. Duau, J. W. Lockwood, and S. M. Kang, "Matrix unit cell scheduler (MUCS) for input-buffered switches," IBEE Communication Letters, vol. 2, pp. 20-23, Jan. 1998.
|
| |
12
|
N. McKeown and A. Mekkittikul, "A practical scheduling algorithm to achieve 100% throughput in input-queued switches," in INFOCOM'98, (San Francisco), Apr. 1998.
|
| |
13
|
|
| |
14
|
W. Westfeldt, "Intemet reconfignrable logic for creating web-enabled devices." Xilinx Xcell, Q1 1999.
|
| |
15
|
S. Kelem, "Virtex configuration architecture advanced user's guide." Xilinx XAPP151, Sept. 1999.
|
CITED BY 8
|
John W. Lockwood , Naji Naufel , Jon S. Turner , David E. Taylor, Reprogrammable network packet processing on the field programmable port extender (FPX), Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.87-93, February 2001, Monterey, California, United States
|
|
|
|
|
|
|
|
Edson L. Horta , John W. Lockwood , David E. Taylor , David Parlour, Dynamic hardware plugins in an FPGA with partial run-time reconfiguration, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
|
|
|
|
|
|
|
|
|
|
|
|
|